From patchwork Fri Apr 22 06:01:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12822781 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA1E5C4332F for ; Fri, 22 Apr 2022 06:02:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1444104AbiDVGFE (ORCPT ); Fri, 22 Apr 2022 02:05:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44206 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1388243AbiDVGE6 (ORCPT ); Fri, 22 Apr 2022 02:04:58 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7C23A4F9FA; Thu, 21 Apr 2022 23:02:06 -0700 (PDT) X-UUID: 8b85303975314f5480bb236e072497fd-20220422 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:64c2704d-c7a6-47b1-b307-63802039946d,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:0 X-CID-META: VersionHash:faefae9,CLOUDID:2c22bdef-06b0-4305-bfbf-554bfc9d151a,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,File:nil,QS:0,BEC:nil X-UUID: 8b85303975314f5480bb236e072497fd-20220422 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1347074194; Fri, 22 Apr 2022 14:02:01 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Fri, 22 Apr 2022 14:02:00 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 22 Apr 2022 14:02:00 +0800 From: Rex-BC Chen To: , , , , CC: , , , , , , , , , , , Rex-BC Chen Subject: [PATCH V3 13/17] dt-bindings: arm: mediatek: Add #reset-cells property for MT8195-sys-clock Date: Fri, 22 Apr 2022 14:01:48 +0800 Message-ID: <20220422060152.13534-14-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220422060152.13534-1-rex-bc.chen@mediatek.com> References: <20220422060152.13534-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org We will use the infra_ao reset which is defined in mt8195-sys-clock. The maximum value of reset-cells is 2. Therefore, we add this patch to define it. Signed-off-by: Rex-BC Chen --- .../bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml index 57a1503d95fe..66b7852ce711 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml @@ -37,6 +37,9 @@ properties: '#clock-cells': const: 1 + '#reset-cells': + maximum: 2 + required: - compatible - reg