From patchwork Fri Apr 22 17:09:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Reichel X-Patchwork-Id: 12823852 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 06936C4332F for ; Fri, 22 Apr 2022 17:11:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1357285AbiDVROc (ORCPT ); Fri, 22 Apr 2022 13:14:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53736 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243610AbiDVRMf (ORCPT ); Fri, 22 Apr 2022 13:12:35 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e3e3]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DA82192320; Fri, 22 Apr 2022 10:09:40 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: sre) with ESMTPSA id 482381F468F5 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1650647377; bh=Lzk2WxbwgXoGe6LfQ+DwZ4F1e/aMgGuJ31kR4qwkhZs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OWEva+EjadbXN0HpKtZw8n7qdqo2Ks3wZYFEL12wYZePzq6XNCDdtxqhftiRW7/O9 Jpo7iTcZafNqHcKQjoVCLs4ROGcsxhotrgXuAlm3WWZQuBDQTVK4+YK7AGQvU7wIXc VUtt4z+V+IWMuJkJwquSa7QMm6TOe+gcgonqgVYkBa6pRIosPGgqzSVA1mbhJIZ5Lr OGubn7x1RS8UB0XxUKdUQkCVDPwuIc4qYbyywo+ozXiJvEPuI9JWrF0WEwUurMQFes PrLKDkbZpq2z05uD/AqXSHp+QcJywOmtfm95JYsxMlypmzdjjISvu8UsyFxKqpIbWq UOLHhpB0hNpEA== Received: by jupiter.universe (Postfix, from userid 1000) id D48AA4807F9; Fri, 22 Apr 2022 19:09:32 +0200 (CEST) From: Sebastian Reichel To: Heiko Stuebner Cc: Rob Herring , Krzysztof Kozlowski , Linus Walleij , Bartosz Golaszewski , Adrian Hunter , Ulf Hansson , Philipp Zabel , Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, linux-mmc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, kernel@lists.collabora.co.uk, Yifeng Zhao , kernel@collabora.com, Sebastian Reichel Subject: [PATCHv1 08/19] mmc: sdhci-of-dwcmshc: add reset call back for rockchip Socs Date: Fri, 22 Apr 2022 19:09:09 +0200 Message-Id: <20220422170920.401914-9-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220422170920.401914-1-sebastian.reichel@collabora.com> References: <20220422170920.401914-1-sebastian.reichel@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org From: Yifeng Zhao The reset function build in the SDHCI will not reset the logic circuit related to the tuning function, which may cause data reading errors. Resetting the complete SDHCI controller through the reset controller fixes the issue. Signed-off-by: Yifeng Zhao [rebase] Signed-off-by: Sebastian Reichel Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci-of-dwcmshc.c | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c index bac874ab0b33..d95ae6ca1256 100644 --- a/drivers/mmc/host/sdhci-of-dwcmshc.c +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include "sdhci-pltfm.h" @@ -63,6 +64,7 @@ struct rk3568_priv { /* Rockchip specified optional clocks */ struct clk_bulk_data rockchip_clks[RK3568_MAX_CLKS]; + struct reset_control *reset; u8 txclk_tapnum; }; @@ -255,6 +257,23 @@ static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN); } +static void rk35xx_sdhci_reset(struct sdhci_host *host, u8 mask) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host); + struct rk35xx_priv *priv = dwc_priv->priv; + + if (mask & SDHCI_RESET_ALL) { + if (!IS_ERR_OR_NULL(priv->reset)) { + reset_control_assert(priv->reset); + udelay(1); + reset_control_deassert(priv->reset); + } + } + + sdhci_reset(host, mask); +} + static const struct sdhci_ops sdhci_dwcmshc_ops = { .set_clock = sdhci_set_clock, .set_bus_width = sdhci_set_bus_width, @@ -269,7 +288,7 @@ static const struct sdhci_ops sdhci_dwcmshc_rk3568_ops = { .set_bus_width = sdhci_set_bus_width, .set_uhs_signaling = dwcmshc_set_uhs_signaling, .get_max_clock = sdhci_pltfm_clk_get_max_clock, - .reset = sdhci_reset, + .reset = rk35xx_sdhci_reset, .adma_write_desc = dwcmshc_adma_write_desc, }; @@ -292,6 +311,13 @@ static int dwcmshc_rk3568_init(struct sdhci_host *host, struct dwcmshc_priv *dwc int err; struct rk3568_priv *priv = dwc_priv->priv; + priv->reset = devm_reset_control_array_get_exclusive(mmc_dev(host->mmc)); + if (IS_ERR_OR_NULL(priv->reset)) { + err = PTR_ERR(priv->reset); + dev_err(mmc_dev(host->mmc), "failed to get reset control %d\n", err); + return err; + } + priv->rockchip_clks[0].id = "axi"; priv->rockchip_clks[1].id = "block"; priv->rockchip_clks[2].id = "timer";