| Message ID | 20220425095244.156720-6-biju.das.jz@bp.renesas.com (mailing list archive) |
|---|---|
| State | Awaiting Upstream, archived |
| Headers | show |
| Series | Add RZ/G2UL CLK and Reset entries for I2C,SSI,USB,CANFD,OSTM and WDT | expand |
Hi Biju, On Mon, Apr 25, 2022 at 11:53 AM Biju Das <biju.das.jz@bp.renesas.com> wrote: > Add OSTM{0,1,2} clock and reset entries to CPG driver. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Thanks for your patch! > --- a/drivers/clk/renesas/r9a07g043-cpg.c > +++ b/drivers/clk/renesas/r9a07g043-cpg.c > @@ -129,6 +129,12 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = { > 0x52c, 0), > DEF_MOD("dmac_pclk", R9A07G043_DMAC_PCLK, CLK_P1_DIV2, > 0x52c, 1), > + DEF_MOD("ostm0", R9A07G043_OSTM0_PCLK, R9A07G043_CLK_P0, > + 0x534, 0), > + DEF_MOD("ostm1", R9A07G043_OSTM1_PCLK, R9A07G043_CLK_P0, > + 0x534, 1), > + DEF_MOD("ostm2", R9A07G043_OSTM2_PCLK, R9A07G043_CLK_P0, > + 0x534, 2), Do you mind if I change the clock names to "ostm[012_pclk" while applying, for consistency with r9a07g044-cpg.c. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-clk-for-v5.19. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Geert, Thanks for the feedback. > Subject: Re: [PATCH 5/6] clk: renesas: r9a07g043: Add OSTM clock and reset > entries > > Hi Biju, > > On Mon, Apr 25, 2022 at 11:53 AM Biju Das <biju.das.jz@bp.renesas.com> > wrote: > > Add OSTM{0,1,2} clock and reset entries to CPG driver. > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > > Thanks for your patch! > > > --- a/drivers/clk/renesas/r9a07g043-cpg.c > > +++ b/drivers/clk/renesas/r9a07g043-cpg.c > > @@ -129,6 +129,12 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = > { > > 0x52c, 0), > > DEF_MOD("dmac_pclk", R9A07G043_DMAC_PCLK, CLK_P1_DIV2, > > 0x52c, 1), > > + DEF_MOD("ostm0", R9A07G043_OSTM0_PCLK, R9A07G043_CLK_P0, > > + 0x534, 0), > > + DEF_MOD("ostm1", R9A07G043_OSTM1_PCLK, R9A07G043_CLK_P0, > > + 0x534, 1), > > + DEF_MOD("ostm2", R9A07G043_OSTM2_PCLK, R9A07G043_CLK_P0, > > + 0x534, 2), > > Do you mind if I change the clock names to "ostm[012_pclk" > while applying, for consistency with r9a07g044-cpg.c. Thanks, Ok for me. Cheers, Biju > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue > in renesas-clk-for-v5.19. > > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux- > m68k.org > > In personal conversations with technical people, I call myself a hacker. > But when I'm talking to journalists I just say "programmer" or something > like that. > -- Linus Torvalds
diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c index 59d5405474a5..ac2b361efbb6 100644 --- a/drivers/clk/renesas/r9a07g043-cpg.c +++ b/drivers/clk/renesas/r9a07g043-cpg.c @@ -129,6 +129,12 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = { 0x52c, 0), DEF_MOD("dmac_pclk", R9A07G043_DMAC_PCLK, CLK_P1_DIV2, 0x52c, 1), + DEF_MOD("ostm0", R9A07G043_OSTM0_PCLK, R9A07G043_CLK_P0, + 0x534, 0), + DEF_MOD("ostm1", R9A07G043_OSTM1_PCLK, R9A07G043_CLK_P0, + 0x534, 1), + DEF_MOD("ostm2", R9A07G043_OSTM2_PCLK, R9A07G043_CLK_P0, + 0x534, 2), DEF_MOD("sdhi0_imclk", R9A07G043_SDHI0_IMCLK, CLK_SD0_DIV4, 0x554, 0), DEF_MOD("sdhi0_imclk2", R9A07G043_SDHI0_IMCLK2, CLK_SD0_DIV4, @@ -211,6 +217,9 @@ static struct rzg2l_reset r9a07g043_resets[] = { DEF_RST(R9A07G043_IA55_RESETN, 0x818, 0), DEF_RST(R9A07G043_DMAC_ARESETN, 0x82c, 0), DEF_RST(R9A07G043_DMAC_RST_ASYNC, 0x82c, 1), + DEF_RST(R9A07G043_OSTM0_PRESETZ, 0x834, 0), + DEF_RST(R9A07G043_OSTM1_PRESETZ, 0x834, 1), + DEF_RST(R9A07G043_OSTM2_PRESETZ, 0x834, 2), DEF_RST(R9A07G043_SDHI0_IXRST, 0x854, 0), DEF_RST(R9A07G043_SDHI1_IXRST, 0x854, 1), DEF_RST(R9A07G043_SSI0_RST_M2_REG, 0x870, 0),
Add OSTM{0,1,2} clock and reset entries to CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- drivers/clk/renesas/r9a07g043-cpg.c | 9 +++++++++ 1 file changed, 9 insertions(+)