| Message ID | 20220427030950.23395-15-rex-bc.chen@mediatek.com (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Headers | show
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From: Rex-BC Chen <rex-bc.chen@mediatek.com>
To: <mturquette@baylibre.com>, <sboyd@kernel.org>,
<matthias.bgg@gmail.com>, <robh+dt@kernel.org>,
<krzysztof.kozlowski+dt@linaro.org>
CC: <p.zabel@pengutronix.de>,
<angelogioacchino.delregno@collabora.com>,
<chun-jie.chen@mediatek.com>, <wenst@chromium.org>,
<runyang.chen@mediatek.com>, <linux-kernel@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-clk@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>,
<Project_Global_Chrome_Upstream_Group@mediatek.com>,
Rex-BC Chen <rex-bc.chen@mediatek.com>
Subject: [PATCH V4 14/15] arm64: dts: mediatek: Add infra #reset-cells
property for MT8192
Date: Wed, 27 Apr 2022 11:09:49 +0800
Message-ID: <20220427030950.23395-15-rex-bc.chen@mediatek.com>
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|
| Series |
Cleanup MediaTek clk reset drivers and support MT8192/MT8195
|
expand
|
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 411feb294613..79803420d8ef 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -269,6 +269,7 @@ compatible = "mediatek,mt8192-infracfg", "syscon"; reg = <0 0x10001000 0 0x1000>; #clock-cells = <1>; + #reset-cells = <1>; }; pericfg: syscon@10003000 {
To support reset of infra, we add the property of #reset-cells. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 1 + 1 file changed, 1 insertion(+)