| Message ID | 20220429151247.388837-7-robert.foss@linaro.org (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Headers | show |
| Series | [v1,1/9] clk: qcom: rcg2: Cache rate changes for parked RCGs | expand |
On 29/04/2022 18:12, Robert Foss wrote: > From: Jonathan Marek <jonathan@marek.ca> > > Add sm8350 DISPCC bindings, which are simply a symlink to the sm8250 > bindings. Update the documentation with the new compatible. > > Signed-off-by: Jonathan Marek <jonathan@marek.ca> > Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > > Due to qcom,dispcc-sm8350.h being a symlink, checkpatch is not happy > with this patch. Other than warnings related to this, it should be good. > > > .../devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml | 6 ++++-- > include/dt-bindings/clock/qcom,dispcc-sm8350.h | 1 + > 2 files changed, 5 insertions(+), 2 deletions(-) > create mode 120000 include/dt-bindings/clock/qcom,dispcc-sm8350.h > > diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml > index 31497677e8de..7a8d375e055e 100644 > --- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml > +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml > @@ -4,18 +4,19 @@ > $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml# > $schema: http://devicetree.org/meta-schemas/core.yaml# > > -title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250 > +title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250/SM8350 > > maintainers: > - Jonathan Marek <jonathan@marek.ca> > > description: | > Qualcomm display clock control module which supports the clocks, resets and > - power domains on SM8150 and SM8250. > + power domains on SM8150/SM8250/SM8350. > > See also: > dt-bindings/clock/qcom,dispcc-sm8150.h > dt-bindings/clock/qcom,dispcc-sm8250.h > + dt-bindings/clock/qcom,dispcc-sm8350.h > > properties: > compatible: > @@ -23,6 +24,7 @@ properties: > - qcom,sc8180x-dispcc > - qcom,sm8150-dispcc > - qcom,sm8250-dispcc > + - qcom,sm8350-dispcc > > clocks: > items: > diff --git a/include/dt-bindings/clock/qcom,dispcc-sm8350.h b/include/dt-bindings/clock/qcom,dispcc-sm8350.h > new file mode 120000 > index 000000000000..0312b4544acb > --- /dev/null > +++ b/include/dt-bindings/clock/qcom,dispcc-sm8350.h > @@ -0,0 +1 @@ > +qcom,dispcc-sm8250.h > \ No newline at end of file
diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml index 31497677e8de..7a8d375e055e 100644 --- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml @@ -4,18 +4,19 @@ $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250 +title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250/SM8350 maintainers: - Jonathan Marek <jonathan@marek.ca> description: | Qualcomm display clock control module which supports the clocks, resets and - power domains on SM8150 and SM8250. + power domains on SM8150/SM8250/SM8350. See also: dt-bindings/clock/qcom,dispcc-sm8150.h dt-bindings/clock/qcom,dispcc-sm8250.h + dt-bindings/clock/qcom,dispcc-sm8350.h properties: compatible: @@ -23,6 +24,7 @@ properties: - qcom,sc8180x-dispcc - qcom,sm8150-dispcc - qcom,sm8250-dispcc + - qcom,sm8350-dispcc clocks: items: diff --git a/include/dt-bindings/clock/qcom,dispcc-sm8350.h b/include/dt-bindings/clock/qcom,dispcc-sm8350.h new file mode 120000 index 000000000000..0312b4544acb --- /dev/null +++ b/include/dt-bindings/clock/qcom,dispcc-sm8350.h @@ -0,0 +1 @@ +qcom,dispcc-sm8250.h \ No newline at end of file