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Mon, 2 May 2022 18:01:01 +0900 (KST) Received: from epsmtrp1.samsung.com (unknown [182.195.40.13]) by epcas2p2.samsung.com (KnoxPortal) with ESMTPA id 20220502090101epcas2p259f09e3ca3ba6361c47d39a66d9fd172~rPi8-AXym0159201592epcas2p2w; Mon, 2 May 2022 09:01:01 +0000 (GMT) Received: from epsmgms1p2.samsung.com (unknown [182.195.42.42]) by epsmtrp1.samsung.com (KnoxPortal) with ESMTP id 20220502090100epsmtrp15d9b78a2373faa30ad8c0e2fd53a978d~rPi8_MOJN2529725297epsmtrp1d; Mon, 2 May 2022 09:01:00 +0000 (GMT) X-AuditID: b6c32a46-f8bff70000002624-eb-626f9dcdb301 Received: from epsmtip2.samsung.com ( [182.195.34.31]) by epsmgms1p2.samsung.com (Symantec Messaging Gateway) with SMTP id 13.FB.08924.CCD9F626; Mon, 2 May 2022 18:01:00 +0900 (KST) Received: from localhost.localdomain (unknown [10.229.9.51]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20220502090100epsmtip20dcd6dbe368d800b0a978db1b1c4e922~rPi8z29PD1979719797epsmtip2U; Mon, 2 May 2022 09:01:00 +0000 (GMT) From: Chanho Park To: Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd , Krzysztof Kozlowski , Rob Herring , Krzysztof Kozlowski Cc: Sam Protsenko , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-samsung-soc@vger.kernel.org, Chanho Park Subject: [PATCH 07/12] clk: samsung: exynosautov9: add cmu_fsys2 clock support Date: Mon, 2 May 2022 18:02:25 +0900 Message-Id: <20220502090230.12853-8-chanho61.park@samsung.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220502090230.12853-1-chanho61.park@samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrIJsWRmVeSWpSXmKPExsWy7bCmme7ZuflJBstaxS0ezNvGZnF5v7bF 9S/PWS3mHznHatH34iGzxd7XW9ktPvbcY7WYcX4fk8XFU64WrXuPsFscftPOavHv2kYWi+d9 QPFVu/4wOvB5vL/Ryu6xc9Zddo9NqzrZPO5c28Pm0bdlFaPH501yAWxR2TYZqYkpqUUKqXnJ +SmZeem2St7B8c7xpmYGhrqGlhbmSgp5ibmptkouPgG6bpk5QMcqKZQl5pQChQISi4uV9O1s ivJLS1IVMvKLS2yVUgtScgrMC/SKE3OLS/PS9fJSS6wMDQyMTIEKE7Iz5s02LtimVLHg8lvm BsYmuS5GTg4JAROJZctnsXUxcnEICexglHi5dQYzSEJI4BOjxM+lBhD2Z0aJDyeMYRpOd01i hmjYxSjxZv9EFgjnI6PE5bVd7CBVbAK6Eluev2IESYgIdDFLXOy7B1bFLLCVUeL4jVlMIFXC AgESa37/BrNZBFQltrw4wQpi8wrYSbx/sRjI5gDaJy/xb3EoSJhTwF7izNbnjBAlghInZz5h AbGZgUqat84GO0lCYCGHRH/vXnaIW10kpl1+ywZhC0u8Or4FKi4l8bK/Dcoullg66xMTRHMD 0AvbfkE1GEvMetbOCHIEs4CmxPpd+hD3KEscuQW1l0+i4/Bfdogwr0RHmxBEo7rEge3TWSBs WYnuOZ9ZIWwPicOrbkJDbhKjxMXbS1knMCrMQvLOLCTvzEJYvICReRWjWGpBcW56arFRgRE8 gpPzczcxgtOultsOxilvP+gdYmTiYDzEKMHBrCTC27YhJ0mINyWxsiq1KD++qDQntfgQoykw rCcyS4km5wMTf15JvKGJpYGJmZmhuZGpgbmSOK9XyoZEIYH0xJLU7NTUgtQimD4mDk6pBqZ1 Pyf++/LuuMqe+cwxEwpXh27Su/LwWV7exyMSAednX8/ZveiRbqCVa/TqrPd9WtOm8LBvN7zu ffom38Tz3QHN501zDaf48xruUopp3vd1pXliccr9NW5Mt2/NEGaYbbjD35Q1Oy04tKY+avdE Bacq/pql4jmmi0/8ZXjCu6nvzYu1HEabVpZ/ZxN1aT2p8/2P4/Y/VqEqqVUXFrFXv/qt9vvA 8xfLO55tin1z1nGDQyJn8L3UKSx80tW3Utx3LPsmactYfH36GaF7Hg/ZOTzfedwJ688zmXXP /t50seWnLtumbHFRi9CfvtR/WuaCnyd5BMR/fKmL5AvaIsy6JXwZ21frwHkFqtccZmQ4VpxV YinOSDTUYi4qTgQAYVU1zUQEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrLLMWRmVeSWpSXmKPExsWy7bCSvO6ZuflJBuseWVg8mLeNzeLyfm2L 61+es1rMP3KO1aLvxUNmi72vt7JbfOy5x2ox4/w+JouLp1wtWvceYbc4/Kad1eLftY0sFs/7 gOKrdv1hdODzeH+jld1j56y77B6bVnWyedy5tofNo2/LKkaPz5vkAtiiuGxSUnMyy1KL9O0S uDLmzTYu2KZUseDyW+YGxia5LkZODgkBE4nTXZOYuxi5OIQEdjBK/Ht7jQ0iISvx7N0Odghb WOJ+yxFWiKL3jBKn381hBUmwCehKbHn+ihEkISIwgVnizZUP7CAOs8BORok7r06BjRIW8JOY vnIOE4jNIqAqseXFCbBuXgE7ifcvFgPZHEAr5CX+LQ4FCXMK2Euc2fqcEcQWAir5ceI+M0S5 oMTJmU9YQGxmoPLmrbOZJzAKzEKSmoUktYCRaRWjZGpBcW56brFhgVFearlecWJucWleul5y fu4mRnCMaGntYNyz6oPeIUYmDsZDjBIczEoivG0bcpKEeFMSK6tSi/Lji0pzUosPMUpzsCiJ 817oOhkvJJCeWJKanZpakFoEk2Xi4JRqYGItLRSqm54Q03nktuKbkx0GR/2tdRQnsae6GbT9 9fTenv9DuiSkzavia97TXUrxrHMWpEk2pu3KbXD1uGoUVV8dc7XBjW3rsema2s97/s9Rbsy8 a7T8743pkuFibKdadk5vWaIvxM73MWjHernQ6C2C/BrbdBwjzZ+t+2XKfXjeW+8v6s1HhHWt lMxW20/fUs4lW+ewnfsQ9+7ohVKT0q9r2m4UDtp1+eh3zX26JWopqfzP0zbvMvzx902cgd/6 xq6Cqms/zPdc/dTKsCaNfevd0E2Cc4+dfOfmysN39ZzYe0FH6d62k5l6gl8CLzT9aj99tEc8 8kbN0gWZZtZPembu7ZBZJ8B0gi9f+tlmJZbijERDLeai4kQA8QcyNAADAAA= X-CMS-MailID: 20220502090101epcas2p259f09e3ca3ba6361c47d39a66d9fd172 X-Msg-Generator: CA X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20220502090101epcas2p259f09e3ca3ba6361c47d39a66d9fd172 References: <20220502090230.12853-1-chanho61.park@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org CMU_FSYS2 is responsible to control clocks of BLK_FSYS2 which includes ufs and ethernet IPs. This patch adds some essential clocks to be controlled by ethernet/ufs drivers instead of listing full clocks. Signed-off-by: Chanho Park Reviewed-by: Krzysztof Kozlowski --- drivers/clk/samsung/clk-exynosautov9.c | 69 ++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/drivers/clk/samsung/clk-exynosautov9.c b/drivers/clk/samsung/clk-exynosautov9.c index 65d769875297..ebc759c18e19 100644 --- a/drivers/clk/samsung/clk-exynosautov9.c +++ b/drivers/clk/samsung/clk-exynosautov9.c @@ -1070,6 +1070,73 @@ static const struct samsung_cmu_info core_cmu_info __initconst = { .clk_name = "dout_clkcmu_core_bus", }; +/* ---- CMU_FSYS2 ---------------------------------------------------------- */ + +/* Register Offset definitions for CMU_FSYS2 (0x17c00000) */ +#define PLL_CON0_MUX_CLKCMU_FSYS2_BUS_USER 0x0600 +#define PLL_CON0_MUX_CLKCMU_FSYS2_UFS_EMBD_USER 0x0620 +#define PLL_CON0_MUX_CLKCMU_FSYS2_ETHERNET_USER 0x0610 +#define CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD0_IPCLKPORT_I_ACLK 0x2098 +#define CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD0_IPCLKPORT_I_CLK_UNIPRO 0x209c +#define CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD1_IPCLKPORT_I_ACLK 0x20a4 +#define CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD1_IPCLKPORT_I_CLK_UNIPRO 0x20a8 + +static const unsigned long fsys2_clk_regs[] __initconst = { + PLL_CON0_MUX_CLKCMU_FSYS2_BUS_USER, + PLL_CON0_MUX_CLKCMU_FSYS2_UFS_EMBD_USER, + PLL_CON0_MUX_CLKCMU_FSYS2_ETHERNET_USER, + CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD0_IPCLKPORT_I_ACLK, + CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD0_IPCLKPORT_I_CLK_UNIPRO, + CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD1_IPCLKPORT_I_ACLK, + CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD1_IPCLKPORT_I_CLK_UNIPRO, +}; + +/* List of parent clocks for Muxes in CMU_FSYS2 */ +PNAME(mout_fsys2_bus_user_p) = { "oscclk", "dout_clkcmu_fsys2_bus" }; +PNAME(mout_fsys2_ufs_embd_user_p) = { "oscclk", "dout_clkcmu_fsys2_ufs_embd" }; +PNAME(mout_fsys2_ethernet_user_p) = { "oscclk", "dout_clkcmu_fsys2_ethernet" }; + +static const struct samsung_mux_clock fsys2_mux_clks[] __initconst = { + MUX(CLK_MOUT_FSYS2_BUS_USER, "mout_fsys2_bus_user", + mout_fsys2_bus_user_p, PLL_CON0_MUX_CLKCMU_FSYS2_BUS_USER, 4, 1), + MUX(CLK_MOUT_FSYS2_UFS_EMBD_USER, "mout_fsys2_ufs_embd_user", + mout_fsys2_ufs_embd_user_p, + PLL_CON0_MUX_CLKCMU_FSYS2_UFS_EMBD_USER, 4, 1), + MUX(CLK_MOUT_FSYS2_ETHERNET_USER, "mout_fsys2_ethernet_user", + mout_fsys2_ethernet_user_p, + PLL_CON0_MUX_CLKCMU_FSYS2_ETHERNET_USER, 4, 1), +}; + +static const struct samsung_gate_clock fsys2_gate_clks[] __initconst = { + GATE(CLK_GOUT_FSYS2_UFS_EMBD0_ACLK, "gout_fsys2_ufs_embd0_aclk", + "mout_fsys2_ufs_embd_user", + CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD0_IPCLKPORT_I_ACLK, 21, + 0, 0), + GATE(CLK_GOUT_FSYS2_UFS_EMBD0_UNIPRO, "gout_fsys2_ufs_embd0_unipro", + "mout_fsys2_ufs_embd_user", + CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD0_IPCLKPORT_I_CLK_UNIPRO, + 21, 0, 0), + GATE(CLK_GOUT_FSYS2_UFS_EMBD1_ACLK, "gout_fsys2_ufs_embd1_aclk", + "mout_fsys2_ufs_embd_user", + CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD1_IPCLKPORT_I_ACLK, 21, + 0, 0), + GATE(CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO, "gout_fsys2_ufs_embd1_unipro", + "mout_fsys2_ufs_embd_user", + CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD1_IPCLKPORT_I_CLK_UNIPRO, + 21, 0, 0), +}; + +static const struct samsung_cmu_info fsys2_cmu_info __initconst = { + .mux_clks = fsys2_mux_clks, + .nr_mux_clks = ARRAY_SIZE(fsys2_mux_clks), + .gate_clks = fsys2_gate_clks, + .nr_gate_clks = ARRAY_SIZE(fsys2_gate_clks), + .nr_clk_ids = FSYS2_NR_CLK, + .clk_regs = fsys2_clk_regs, + .nr_clk_regs = ARRAY_SIZE(fsys2_clk_regs), + .clk_name = "dout_clkcmu_fsys2_bus", +}; + /* ---- CMU_PERIS ---------------------------------------------------------- */ /* Register Offset definitions for CMU_PERIS (0x10020000) */ @@ -1136,6 +1203,8 @@ static const struct of_device_id exynosautov9_cmu_of_match[] = { .compatible = "samsung,exynosautov9-cmu-core", .data = &core_cmu_info, }, { + .compatible = "samsung,exynosautov9-cmu-fsys2", + .data = &fsys2_cmu_info, }, { .compatible = "samsung,exynosautov9-cmu-peris", .data = &peris_cmu_info,