| Message ID | 20220503093856.22250-16-rex-bc.chen@mediatek.com (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Headers | show |
| Series | Cleanup MediaTek clk reset drivers and support MT8192/MT8195 | expand |
On 03/05/2022 11:38, Rex-BC Chen wrote: > To support reset of infra, we add property of #reset-cells. > > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> > Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Applied, thanks! > --- > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > index 411feb294613..79803420d8ef 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > @@ -269,6 +269,7 @@ > compatible = "mediatek,mt8192-infracfg", "syscon"; > reg = <0 0x10001000 0 0x1000>; > #clock-cells = <1>; > + #reset-cells = <1>; > }; > > pericfg: syscon@10003000 {
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 411feb294613..79803420d8ef 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -269,6 +269,7 @@ compatible = "mediatek,mt8192-infracfg", "syscon"; reg = <0 0x10001000 0 0x1000>; #clock-cells = <1>; + #reset-cells = <1>; }; pericfg: syscon@10003000 {