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Wed, 4 May 2022 16:50:04 +0900 (KST) Received: from epsmtrp1.samsung.com (unknown [182.195.40.13]) by epcas2p1.samsung.com (KnoxPortal) with ESMTPA id 20220504075003epcas2p17f37265b522bb0c26dbdd4ebeec92ab9~r13ksGvzO2925229252epcas2p1U; Wed, 4 May 2022 07:50:03 +0000 (GMT) Received: from epsmgms1p2.samsung.com (unknown [182.195.42.42]) by epsmtrp1.samsung.com (KnoxPortal) with ESMTP id 20220504075003epsmtrp1b63541ef978f110babe8c646c4772202~r13krR7-52992129921epsmtrp1T; Wed, 4 May 2022 07:50:03 +0000 (GMT) X-AuditID: b6c32a48-47fff700000025de-dc-6272302ca1cc Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgms1p2.samsung.com (Symantec Messaging Gateway) with SMTP id E7.EB.08924.B2032726; Wed, 4 May 2022 16:50:03 +0900 (KST) Received: from localhost.localdomain (unknown [10.229.9.51]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20220504075003epsmtip170892b3f55e240eb049d16c2f832b94c~r13keC7xN2390523905epsmtip1B; Wed, 4 May 2022 07:50:03 +0000 (GMT) From: Chanho Park To: Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd , Krzysztof Kozlowski , Rob Herring , Krzysztof Kozlowski Cc: Sam Protsenko , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-samsung-soc@vger.kernel.org, Chanho Park Subject: [PATCH v3 02/12] dt-bindings: clock: add Exynos Auto v9 SoC CMU bindings Date: Wed, 4 May 2022 16:51:44 +0900 Message-Id: <20220504075154.58819-3-chanho61.park@samsung.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220504075154.58819-1-chanho61.park@samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrEJsWRmVeSWpSXmKPExsWy7bCmma6OQVGSwfOzPBYP5m1js7i8X9vi +pfnrBbzj5xjteh78ZDZYu/rrewWH3vusVrMOL+PyeLiKVeL1r1H2C0Ov2lntfh3bSOLxfM+ oPiqXX8YHfg83t9oZffYOesuu8emVZ1sHneu7WHz6NuyitHj8ya5ALaobJuM1MSU1CKF1Lzk /JTMvHRbJe/geOd4UzMDQ11DSwtzJYW8xNxUWyUXnwBdt8wcoGOVFMoSc0qBQgGJxcVK+nY2 RfmlJakKGfnFJbZKqQUpOQXmBXrFibnFpXnpenmpJVaGBgZGpkCFCdkZU9q3sBRcMK243D6R uYHxq0oXIweHhICJxJVOqy5GLg4hgR2MEq+XbmOEcD4xSqx5PoMdwvnMKLGqfxeQwwnW8btl JjNEYhejxIpV86Gcj4wSmzasYwOpYhPQldjy/BXYLBGBLmaJi333WEAcZoGtjBLHb8xiAqkS FgiWmPvjIiOIzSKgKnHr2x6wbl4BO4l1L7tZIS6Ul/i3OBTE5BSwl3i8wQKiQlDi5MwnLCA2 M1BF89bZYEdICCzkkPh0/C3UqS4Sj2cvgLKFJV4d3wJlS0m87G+Dsoslls76xATR3MAocXnb LzaIhLHErGftjCCLmQU0Jdbv0oc4R1niyC2ovXwSHYf/skOEeSU62oQgGtUlDmyfzgJhy0p0 z/nMCmF7SFyatRAavJOAofDkEuMERoVZSN6ZheSdWQiLFzAyr2IUSy0ozk1PLTYqMIHHcHJ+ 7iZGcOLV8tjBOPvtB71DjEwcjIcYJTiYlUR4nZcWJAnxpiRWVqUW5ccXleakFh9iNAUG9URm KdHkfGDqzyuJNzSxNDAxMzM0NzI1MFcS5/VK2ZAoJJCeWJKanZpakFoE08fEwSnVwCSRk55Y 2zlP5ytzDFuxYfzPJ2aHSv8bC8ezSRT94yoLeLqSbVXJoroNrrNY+hueyAZr/bxf43zx/OkV /sURfK1Ozv92ulxjeJYVq/t56pGj+x69mLGpU+DJ+YpT92p2rv9/Oa97/ZEZs6dxLukKMvOq vtxmq6G1ZFpphOGPO68/zzmiwuKq6ZVb/z5+SdycveKzBRwr/iybyyn0g/04hxaPXdOiHS72 ETl8reu2tHOKr7kb737kyAt5uV2i98qXsede17vb/UvA+9T0NcUrefLPiHXOXOP3OmkDg6LR ifuREw3/HZ5/4XKS+wWtJ2f0rl74xseY6vpfWmtL1r2lj+6UL9I94uazjWeTOzdbYI8SS3FG oqEWc1FxIgCe1HVmRQQAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrNLMWRmVeSWpSXmKPExsWy7bCSnK62QVGSQfN/TYsH87axWVzer21x /ctzVov5R86xWvS9eMhssff1VnaLjz33WC1mnN/HZHHxlKtF694j7BaH37SzWvy7tpHF4nkf UHzVrj+MDnwe72+0snvsnHWX3WPTqk42jzvX9rB59G1ZxejxeZNcAFsUl01Kak5mWWqRvl0C V8aU9i0sBRdMKy63T2RuYPyq0sXIySEhYCLxu2UmcxcjF4eQwA5GiYftE1kgErISz97tYIew hSXutxxhBbGFBN4zSjx4ZQxiswnoSmx5/ooRpFlEYAKzxJsrH9hBHGaBnYwSd16dYgOpEhYI lGjubwSbxCKgKnHr2x6wOK+AncS6l91AUzmANshL/FscCmJyCthLPN5gAWIKAVUcnVQEUSwo cXLmE7DTmIGKm7fOZp7AKDALSWoWktQCRqZVjJKpBcW56bnFhgVGeanlesWJucWleel6yfm5 mxjB8aGltYNxz6oPeocYmTgYDzFKcDArifA6Ly1IEuJNSaysSi3Kjy8qzUktPsQozcGiJM57 oetkvJBAemJJanZqakFqEUyWiYNTqoFp3jPWY8ESyxIVbE+2JlWVHtv84fmqPC3LnZ+e9/kZ TCs5HOQ6/WLkUyHhCQ3Su6xl1X4sUMyfVyW1XGv/rTtXn75IzOy+7Z3E+3auyaGzxRsCn7l+ 2xkTk1/1cXvFpaKCbcaTJA9eNOlbsXlWn+DlQ1Eub9KMXqkwXVBgvXKxact5fosSxvSNzNt7 T9q9vnak/bpDzb0JN1k/mplZBtfYCG1Vfr19ofLtI2zbrB9cSJu77qtGbn+SSt4Hvo1L0qwC Jh1SF7EIPbfz5/rqGy+kQ+p4LnCd2nHgh9W0BVcX+2Xo8dk/u8x8yLBnwn2B3zEcG5zZrlp+ qkj/91dFvdbp3Zu9NXuXPLh/64V51vzjG5VYijMSDbWYi4oTAYPOHu3+AgAA X-CMS-MailID: 20220504075003epcas2p17f37265b522bb0c26dbdd4ebeec92ab9 X-Msg-Generator: CA X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20220504075003epcas2p17f37265b522bb0c26dbdd4ebeec92ab9 References: <20220504075154.58819-1-chanho61.park@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add dt-schema for Exynos Auto v9 SoC clock controller. Signed-off-by: Chanho Park Reviewed-by: Krzysztof Kozlowski Reviewed-by: Chanwoo Choi --- .../clock/samsung,exynosautov9-clock.yaml | 219 ++++++++++++++++++ 1 file changed, 219 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml diff --git a/Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml new file mode 100644 index 000000000000..eafc715d2d02 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml @@ -0,0 +1,219 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/samsung,exynosautov9-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos Auto v9 SoC clock controller + +maintainers: + - Chanho Park + - Chanwoo Choi + - Krzysztof Kozlowski + - Sylwester Nawrocki + - Tomasz Figa + +description: | + Exynos Auto v9 clock controller is comprised of several CMU units, generating + clocks for different domains. Those CMU units are modeled as separate device + tree nodes, and might depend on each other. Root clocks in that clock tree are + two external clocks:: OSCCLK/XTCXO (26 MHz) and RTCCLK/XrtcXTI (32768 Hz). + The external OSCCLK must be defined as fixed-rate clock in dts. + + CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and + dividers; all other clocks of function blocks (other CMUs) are usually + derived from CMU_TOP. + + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All clocks available for usage + in clock consumer nodes are defined as preprocessor macros in + 'include/dt-bindings/clock/samsung,exynosautov9.h' header. + +properties: + compatible: + enum: + - samsung,exynosautov9-cmu-top + - samsung,exynosautov9-cmu-busmc + - samsung,exynosautov9-cmu-core + - samsung,exynosautov9-cmu-fsys2 + - samsung,exynosautov9-cmu-peric0 + - samsung,exynosautov9-cmu-peric1 + - samsung,exynosautov9-cmu-peris + + clocks: + minItems: 1 + maxItems: 5 + + clock-names: + minItems: 1 + maxItems: 5 + + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + +allOf: + - if: + properties: + compatible: + contains: + const: samsung,exynosautov9-cmu-top + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + + clock-names: + items: + - const: oscclk + + - if: + properties: + compatible: + contains: + const: samsung,exynosautov9-cmu-busmc + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_BUSMC bus clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_clkcmu_busmc_bus + + - if: + properties: + compatible: + contains: + const: samsung,exynosautov9-cmu-core + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_CORE bus clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_clkcmu_core_bus + + - if: + properties: + compatible: + contains: + const: samsung,exynosautov9-cmu-fsys2 + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_FSYS2 bus clock (from CMU_TOP) + - description: UFS clock (from CMU_TOP) + - description: Ethernet clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_clkcmu_fsys2_bus + - const: dout_fsys2_clkcmu_ufs_embd + - const: dout_fsys2_clkcmu_ethernet + + - if: + properties: + compatible: + contains: + const: samsung,exynosautov9-cmu-peric0 + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_PERIC0 bus clock (from CMU_TOP) + - description: PERIC0 IP clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_clkcmu_peric0_bus + - const: dout_clkcmu_peric0_ip + + - if: + properties: + compatible: + contains: + const: samsung,exynosautov9-cmu-peric1 + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_PERIC1 bus clock (from CMU_TOP) + - description: PERIC1 IP clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_clkcmu_peric1_bus + - const: dout_clkcmu_peric1_ip + + - if: + properties: + compatible: + contains: + const: samsung,exynosautov9-cmu-peris + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_PERIS bus clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_clkcmu_peris_bus + +required: + - compatible + - "#clock-cells" + - clocks + - clock-names + - reg + +additionalProperties: false + +examples: + # Clock controller node for CMU_FSYS2 + - | + #include + + cmu_fsys2: clock-controller@17c00000 { + compatible = "samsung,exynosautov9-cmu-fsys2"; + reg = <0x17c00000 0x8000>; + #clock-cells = <1>; + + clocks = <&xtcxo>, + <&cmu_top DOUT_CLKCMU_FSYS2_BUS>, + <&cmu_top DOUT_CLKCMU_FSYS2_UFS_EMBD>, + <&cmu_top DOUT_CLKCMU_FSYS2_ETHERNET>; + clock-names = "oscclk", + "dout_clkcmu_fsys2_bus", + "dout_fsys2_clkcmu_ufs_embd", + "dout_fsys2_clkcmu_ethernet"; + }; + +...