| Message ID | 20220520094323.754971-5-wenst@chromium.org (mailing list archive) |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | clk: mediatek: mt8183: Fix GPU/MFG clock rate changing | expand |
Quoting Chen-Yu Tsai (2022-05-20 02:43:23) > diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c > index 8a755fadebb5..afef3738396e 100644 > --- a/drivers/clk/mediatek/clk-mt8183.c > +++ b/drivers/clk/mediatek/clk-mt8183.c > @@ -1217,6 +1219,25 @@ static int clk_mt8183_top_probe(struct platform_device *pdev) > mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), > top_clk_data); > > + /* Register mux notifier for MFG mux */ This comment sort of indicates it should be another function for this block called "register mfg mux notifier". > + mfg_mux_nb = devm_kzalloc(&pdev->dev, sizeof(*mfg_mux_nb), GFP_KERNEL); > + if (!mfg_mux_nb) > + return -ENOMEM; > + > + for (i = 0; i < ARRAY_SIZE(top_muxes); i++) > + if (top_muxes[i].id == CLK_TOP_MUX_MFG) > + break; > + if (i == ARRAY_SIZE(top_muxes)) > + return -EINVAL; > + > + mfg_mux_nb->mux = &top_muxes[i]; > + mfg_mux_nb->bypass_index = 0; // Bypass to 26M crystal Use /* these types of comments */ > + ret = devm_mtk_clk_mux_notifier_register(&pdev->dev, > + top_clk_data->hws[CLK_TOP_MUX_MFG]->clk, > + mfg_mux_nb); > + if (ret) > + return ret; > + > return of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c index 8a755fadebb5..afef3738396e 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -1192,6 +1192,8 @@ static int clk_mt8183_top_probe(struct platform_device *pdev) { void __iomem *base; struct device_node *node = pdev->dev.of_node; + struct mtk_mux_nb *mfg_mux_nb; + int i, ret; base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base)) @@ -1217,6 +1219,25 @@ static int clk_mt8183_top_probe(struct platform_device *pdev) mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), top_clk_data); + /* Register mux notifier for MFG mux */ + mfg_mux_nb = devm_kzalloc(&pdev->dev, sizeof(*mfg_mux_nb), GFP_KERNEL); + if (!mfg_mux_nb) + return -ENOMEM; + + for (i = 0; i < ARRAY_SIZE(top_muxes); i++) + if (top_muxes[i].id == CLK_TOP_MUX_MFG) + break; + if (i == ARRAY_SIZE(top_muxes)) + return -EINVAL; + + mfg_mux_nb->mux = &top_muxes[i]; + mfg_mux_nb->bypass_index = 0; // Bypass to 26M crystal + ret = devm_mtk_clk_mux_notifier_register(&pdev->dev, + top_clk_data->hws[CLK_TOP_MUX_MFG]->clk, + mfg_mux_nb); + if (ret) + return ret; + return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data); }
When the MFG PLL clock, which is upstream of the MFG clock, is changed, the downstream clock and consumers need to be switched away from the PLL over to a stable clock to avoid glitches. This is done through the use of the newly added clk mux notifier. The notifier is set on the mux itself instead of the upstream PLL, but in practice this works, as the rate change notifitcations are propogated throughout the sub-tree hanging off the PLL. Just before rate changes, the MFG mux is temporarily and transparently switched to the 26 MHz main crystal. After the rate change, the mux is switched back. Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> --- drivers/clk/mediatek/clk-mt8183.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+)