| Message ID | 20220617093424.75589-3-angelogioacchino.delregno@collabora.com (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Headers | show |
| Series | MediaTek Kompanio 1200 MT8195 - DisplayPort clocks fixes | expand |
On Fri, 2022-06-17 at 17:34 +0800, AngeloGioacchino Del Regno wrote: > Like it was done for the vdo0_dp_intf0_dp_intf clock (used for eDP), > add the CLK_SET_RATE_PARENT flag to CLK_VDO1_DPINTF (used for DP) > and also fix its parent clock name as it has to be "top_dp" for two > reasons: > - This is its real parent! > - Likewise to eDP/VDO0 counterpart, we need clock source > selection on CLK_TOP_DP. > > Signed-off-by: AngeloGioacchino Del Regno < > angelogioacchino.delregno@collabora.com> > Fixes: 269987505ba9 ("clk: mediatek: Add MT8195 vdosys1 clock > support") > Hello Angelo, Thanks for this series. I can use this series to do modetest using MT8195 Tomato Chromebook for both dp and edp in kernel v5.19-rc1. Therefore, Tested-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> and, Reviewed-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> BRs, Bo-Chen
diff --git a/drivers/clk/mediatek/clk-mt8195-vdo1.c b/drivers/clk/mediatek/clk-mt8195-vdo1.c index 3378487d2c90..d54d7726d186 100644 --- a/drivers/clk/mediatek/clk-mt8195-vdo1.c +++ b/drivers/clk/mediatek/clk-mt8195-vdo1.c @@ -43,6 +43,10 @@ static const struct mtk_gate_regs vdo1_3_cg_regs = { #define GATE_VDO1_2(_id, _name, _parent, _shift) \ GATE_MTK(_id, _name, _parent, &vdo1_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr) +#define GATE_VDO1_2_FLAGS(_id, _name, _parent, _shift, _flags) \ + GATE_MTK_FLAGS(_id, _name, _parent, &vdo1_2_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr, _flags) + #define GATE_VDO1_3(_id, _name, _parent, _shift) \ GATE_MTK(_id, _name, _parent, &vdo1_3_cg_regs, _shift, &mtk_clk_gate_ops_setclr) @@ -99,7 +103,7 @@ static const struct mtk_gate vdo1_clks[] = { GATE_VDO1_2(CLK_VDO1_DISP_MONITOR_DPI0, "vdo1_disp_monitor_dpi0", "top_vpp", 1), GATE_VDO1_2(CLK_VDO1_DPI1, "vdo1_dpi1", "top_vpp", 8), GATE_VDO1_2(CLK_VDO1_DISP_MONITOR_DPI1, "vdo1_disp_monitor_dpi1", "top_vpp", 9), - GATE_VDO1_2(CLK_VDO1_DPINTF, "vdo1_dpintf", "top_vpp", 16), + GATE_VDO1_2_FLAGS(CLK_VDO1_DPINTF, "vdo1_dpintf", "top_dp", 16, CLK_SET_RATE_PARENT), GATE_VDO1_2(CLK_VDO1_DISP_MONITOR_DPINTF, "vdo1_disp_monitor_dpintf", "top_vpp", 17), /* VDO1_3 */ GATE_VDO1_3(CLK_VDO1_26M_SLOW, "vdo1_26m_slow", "clk26m", 8),
Like it was done for the vdo0_dp_intf0_dp_intf clock (used for eDP), add the CLK_SET_RATE_PARENT flag to CLK_VDO1_DPINTF (used for DP) and also fix its parent clock name as it has to be "top_dp" for two reasons: - This is its real parent! - Likewise to eDP/VDO0 counterpart, we need clock source selection on CLK_TOP_DP. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Fixes: 269987505ba9 ("clk: mediatek: Add MT8195 vdosys1 clock support") --- drivers/clk/mediatek/clk-mt8195-vdo1.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)