| Message ID | 20220627085632.23797-4-angelogioacchino.delregno@collabora.com (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Headers | show |
| Series | MediaTek Helio X10 MT6795 - Clock drivers | expand |
On 27/06/2022 10:56, AngeloGioacchino Del Regno wrote: > Add the reset controller bindings for MT6795. > > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > Acked-by: Rob Herring <robh@kernel.org> > --- > include/dt-bindings/reset/mt6795-resets.h | 50 +++++++++++++++++++++++ > 1 file changed, 50 insertions(+) > create mode 100644 include/dt-bindings/reset/mt6795-resets.h > > diff --git a/include/dt-bindings/reset/mt6795-resets.h b/include/dt-bindings/reset/mt6795-resets.h > new file mode 100644 > index 000000000000..0a6514884eae > --- /dev/null > +++ b/include/dt-bindings/reset/mt6795-resets.h You still need vendor prefix. Best regards, Krzysztof
Il 29/06/22 12:49, Krzysztof Kozlowski ha scritto: > On 27/06/2022 10:56, AngeloGioacchino Del Regno wrote: >> Add the reset controller bindings for MT6795. >> >> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> >> Acked-by: Rob Herring <robh@kernel.org> >> --- >> include/dt-bindings/reset/mt6795-resets.h | 50 +++++++++++++++++++++++ >> 1 file changed, 50 insertions(+) >> create mode 100644 include/dt-bindings/reset/mt6795-resets.h >> >> diff --git a/include/dt-bindings/reset/mt6795-resets.h b/include/dt-bindings/reset/mt6795-resets.h >> new file mode 100644 >> index 000000000000..0a6514884eae >> --- /dev/null >> +++ b/include/dt-bindings/reset/mt6795-resets.h > > You still need vendor prefix. > > Ouch, I'm sorry, I was somehow convinced that I had added it. v5 coming as soon as I can. Sorry again, Angelo
diff --git a/include/dt-bindings/reset/mt6795-resets.h b/include/dt-bindings/reset/mt6795-resets.h new file mode 100644 index 000000000000..0a6514884eae --- /dev/null +++ b/include/dt-bindings/reset/mt6795-resets.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) */ +/* + * Copyright (c) 2022 Collabora Ltd. + * Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> + */ + +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT6795 +#define _DT_BINDINGS_RESET_CONTROLLER_MT6795 + +/* INFRACFG resets */ +#define MT6795_INFRA_SCPSYS_RST 0 +#define MT6795_INFRA_PMIC_WRAP_RST 1 + +/* MMSYS resets */ +#define MT6795_MMSYS_SW0_RST_B_SMI_COMMON 0 +#define MT6795_MMSYS_SW0_RST_B_SMI_LARB 1 +#define MT6795_MMSYS_SW0_RST_B_CAM_MDP 2 +#define MT6795_MMSYS_SW0_RST_B_MDP_RDMA0 3 +#define MT6795_MMSYS_SW0_RST_B_MDP_RDMA1 4 +#define MT6795_MMSYS_SW0_RST_B_MDP_RSZ0 5 +#define MT6795_MMSYS_SW0_RST_B_MDP_RSZ1 6 +#define MT6795_MMSYS_SW0_RST_B_MDP_RSZ2 7 +#define MT6795_MMSYS_SW0_RST_B_MDP_TDSHP0 8 +#define MT6795_MMSYS_SW0_RST_B_MDP_TDSHP1 9 +#define MT6795_MMSYS_SW0_RST_B_MDP_WDMA 10 +#define MT6795_MMSYS_SW0_RST_B_MDP_WROT0 11 +#define MT6795_MMSYS_SW0_RST_B_MDP_WROT1 12 +#define MT6795_MMSYS_SW0_RST_B_MDP_CROP 13 + +/* PERICFG resets */ +#define MT6795_PERI_NFI_SW_RST 0 +#define MT6795_PERI_THERM_SW_RST 1 +#define MT6795_PERI_MSDC1_SW_RST 2 + +/* TOPRGU resets */ +#define MT6795_TOPRGU_INFRA_SW_RST 0 +#define MT6795_TOPRGU_MM_SW_RST 1 +#define MT6795_TOPRGU_MFG_SW_RST 2 +#define MT6795_TOPRGU_VENC_SW_RST 3 +#define MT6795_TOPRGU_VDEC_SW_RST 4 +#define MT6795_TOPRGU_IMG_SW_RST 5 +#define MT6795_TOPRGU_DDRPHY_SW_RST 6 +#define MT6795_TOPRGU_MD_SW_RST 7 +#define MT6795_TOPRGU_INFRA_AO_SW_RST 8 +#define MT6795_TOPRGU_MD_LITE_SW_RST 9 +#define MT6795_TOPRGU_APMIXED_SW_RST 10 +#define MT6795_TOPRGU_PWRAP_SPI_CTL_RST 11 +#define MT6795_TOPRGU_SW_RST_NUM 12 + +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT6795 */