| Message ID | 20220629105205.173471-3-angelogioacchino.delregno@collabora.com (mailing list archive) |
|---|---|
| State | Accepted, archived |
| Headers | show |
| Series | MT8195: Add resets for PCIe controllers | expand |
Quoting AngeloGioacchino Del Regno (2022-06-29 03:52:05) > Add the reset idx for PCIe P0, P1, located in infra_ao RST2 registers. > > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > --- Applied to clk-next
diff --git a/drivers/clk/mediatek/clk-mt8195-infra_ao.c b/drivers/clk/mediatek/clk-mt8195-infra_ao.c index 97657f255618..ce7ac16a2f42 100644 --- a/drivers/clk/mediatek/clk-mt8195-infra_ao.c +++ b/drivers/clk/mediatek/clk-mt8195-infra_ao.c @@ -193,6 +193,8 @@ static u16 infra_ao_rst_ofs[] = { static u16 infra_ao_idx_map[] = { [MT8195_INFRA_RST0_THERM_CTRL_SWRST] = 0 * RST_NR_PER_BANK + 0, + [MT8195_INFRA_RST2_PCIE_P0_SWRST] = 2 * RST_NR_PER_BANK + 26, + [MT8195_INFRA_RST2_PCIE_P1_SWRST] = 2 * RST_NR_PER_BANK + 27, [MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST] = 3 * RST_NR_PER_BANK + 5, [MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST] = 4 * RST_NR_PER_BANK + 10, };
Add the reset idx for PCIe P0, P1, located in infra_ao RST2 registers. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> --- drivers/clk/mediatek/clk-mt8195-infra_ao.c | 2 ++ 1 file changed, 2 insertions(+)