| Message ID | 20220711104719.40939-1-robimarko@gmail.com (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Headers | show |
| Series | [1/6] clk: qcom: clk-rcg2: add rcg2 mux ops | expand |
On Mon, 11 Jul 2022 at 14:22, Robert Marko <robimarko@gmail.com> wrote: > > From: Christian Marangi <ansuelsmth@gmail.com> > > An RCG may act as a mux that switch between 2 parents. > This is the case on IPQ6018 and IPQ8074 where the APCS core clk that feeds > the CPU cluster clock just switches between XO and the PLL that feeds it. > > Add the required ops to add support for this special configuration and use > the generic mux function to determine the rate. > > This way we dont have to keep a essentially dummy frequency table to use > RCG2 as a mux. > > Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> > Signed-off-by: Robert Marko <robimarko@gmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > drivers/clk/qcom/clk-rcg.h | 1 + > drivers/clk/qcom/clk-rcg2.c | 7 +++++++ > 2 files changed, 8 insertions(+) > > diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h > index 012e745794fd..01581f4d2c39 100644 > --- a/drivers/clk/qcom/clk-rcg.h > +++ b/drivers/clk/qcom/clk-rcg.h > @@ -167,6 +167,7 @@ struct clk_rcg2_gfx3d { > > extern const struct clk_ops clk_rcg2_ops; > extern const struct clk_ops clk_rcg2_floor_ops; > +extern const struct clk_ops clk_rcg2_mux_closest_ops; > extern const struct clk_ops clk_edp_pixel_ops; > extern const struct clk_ops clk_byte_ops; > extern const struct clk_ops clk_byte2_ops; > diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c > index 28019edd2a50..609c10f8d0d9 100644 > --- a/drivers/clk/qcom/clk-rcg2.c > +++ b/drivers/clk/qcom/clk-rcg2.c > @@ -509,6 +509,13 @@ const struct clk_ops clk_rcg2_floor_ops = { > }; > EXPORT_SYMBOL_GPL(clk_rcg2_floor_ops); > > +const struct clk_ops clk_rcg2_mux_closest_ops = { > + .determine_rate = __clk_mux_determine_rate_closest, > + .get_parent = clk_rcg2_get_parent, > + .set_parent = clk_rcg2_set_parent, > +}; > +EXPORT_SYMBOL_GPL(clk_rcg2_mux_closest_ops); > + > struct frac_entry { > int num; > int den; > -- > 2.36.1 >
diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h index 012e745794fd..01581f4d2c39 100644 --- a/drivers/clk/qcom/clk-rcg.h +++ b/drivers/clk/qcom/clk-rcg.h @@ -167,6 +167,7 @@ struct clk_rcg2_gfx3d { extern const struct clk_ops clk_rcg2_ops; extern const struct clk_ops clk_rcg2_floor_ops; +extern const struct clk_ops clk_rcg2_mux_closest_ops; extern const struct clk_ops clk_edp_pixel_ops; extern const struct clk_ops clk_byte_ops; extern const struct clk_ops clk_byte2_ops; diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index 28019edd2a50..609c10f8d0d9 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -509,6 +509,13 @@ const struct clk_ops clk_rcg2_floor_ops = { }; EXPORT_SYMBOL_GPL(clk_rcg2_floor_ops); +const struct clk_ops clk_rcg2_mux_closest_ops = { + .determine_rate = __clk_mux_determine_rate_closest, + .get_parent = clk_rcg2_get_parent, + .set_parent = clk_rcg2_set_parent, +}; +EXPORT_SYMBOL_GPL(clk_rcg2_mux_closest_ops); + struct frac_entry { int num; int den;