From patchwork Sat Jul 23 20:43:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 12927334 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 617D7C43334 for ; Sat, 23 Jul 2022 20:44:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238341AbiGWUog (ORCPT ); Sat, 23 Jul 2022 16:44:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46968 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230301AbiGWUoc (ORCPT ); Sat, 23 Jul 2022 16:44:32 -0400 Received: from mail-pl1-x633.google.com (mail-pl1-x633.google.com [IPv6:2607:f8b0:4864:20::633]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 725241BE88 for ; Sat, 23 Jul 2022 13:44:31 -0700 (PDT) Received: by mail-pl1-x633.google.com with SMTP id g17so7248307plh.2 for ; Sat, 23 Jul 2022 13:44:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=edgeble-ai.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AI3hnw6GQst6wMLXzrihn+hd6U/jUuMJfevBUHROELE=; b=lVzHs3rolZvJFaqy/ykX/EK/UVzyUAQG+ZlAhRXyb4OMUVWki3p6eZa/WkSO8qHUw+ KbIH+Y0+06ZFciOq2E/reLcwUHteaaJQ6Fet6Zv3+ZPJ9ZfMikE7LWu3Z4UOzCzP7ZC8 x6vcqAO6eOzV4D94vcQTxEuBoSBugHhsCS+vNm4SKc6SXouRkqTRjezc54Hli6XU5SBf aHISBNOkfLTgAYtE/0OR4W3epfO1cABRs+AU/dssoj1Tnkc4LdoQMXhO5Yjek8KAqRNO 0374KmerPd1ka1a/Mq/G4kFpmpHN/T5t2cTAijc96/AsOUxZ+P+b2QSaSw9qGV19RujS r3pA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AI3hnw6GQst6wMLXzrihn+hd6U/jUuMJfevBUHROELE=; b=IPJ6jFgOt/U3fFtNiCU3IbTXuSdtY7GZed3ydyk6G0mqucbFIbuketpsc92Gf4QC+5 W+haXERO0z5QYPECfgllVeXrjzwwe2+Pv50N8AaNVZkScP1VO4X8EmQsBKukIVY17RNQ eAF1TbAajgmJPeyaNXkK+yWLngZVJiDbHbi699UtHDNO64kExVV0OkiyS7qlc4EG6O5C TJOVmf1I45MRxZbVGW+u3RefIHcUxA+KzII/dW0zPSZJEeXXtJEhhG8oJ45GvwhOfHJM aPj//8Fw78zqVCn5Rj1KopJ/5IXwg7hi9acUqy4hXGn9N1Ekugd7Wl7li5KtpUHni+XK G80w== X-Gm-Message-State: AJIora8ttsQd+GNajpOQw4YNPz77n+cxtu7co3KEx0FII59fXVt/rTj0 Mr2T11UvnQnyY0n6EBWTQ3DYEA== X-Google-Smtp-Source: AGRyM1uEaWfeyll9tqTyemxevW+UC6MQUUhhMa0jWh6eD9Mo1/y+0SMbCJDJyliC2AzISHWuHvVhpQ== X-Received: by 2002:a17:902:ccc4:b0:156:5d37:b42f with SMTP id z4-20020a170902ccc400b001565d37b42fmr5778156ple.157.1658609070929; Sat, 23 Jul 2022 13:44:30 -0700 (PDT) Received: from localhost.localdomain ([2405:201:c00a:a073:a406:cc30:f4ec:f10a]) by smtp.gmail.com with ESMTPSA id u14-20020a170902e80e00b0016a6caacaefsm6187950plg.103.2022.07.23.13.44.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 23 Jul 2022 13:44:30 -0700 (PDT) From: Jagan Teki To: Heiko Stuebner , Rob Herring , Krzysztof Kozlowski , Kever Yang Cc: linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, Elaine Zhang , linux-clk@vger.kernel.org, Michael Turquette , Stephen Boyd , Jagan Teki Subject: [PATCH 08/22] clk: rockchip: Add MUXTBL variant Date: Sun, 24 Jul 2022 02:13:21 +0530 Message-Id: <20220723204335.750095-9-jagan@edgeble.ai> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220723204335.750095-1-jagan@edgeble.ai> References: <20220723204335.750095-1-jagan@edgeble.ai> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org From: Elaine Zhang A clock branch consisting of a mux with non-standard select values. The parent in Mux table is sorted by priority. Cc: linux-clk@vger.kernel.org Cc: Michael Turquette Cc: Stephen Boyd Signed-off-by: Elaine Zhang Signed-off-by: Jagan Teki --- drivers/clk/rockchip/clk.c | 27 +++++++++++++++++++++------ drivers/clk/rockchip/clk.h | 17 +++++++++++++++++ 2 files changed, 38 insertions(+), 6 deletions(-) diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c index bb8a844309bf..e63d4f20b479 100644 --- a/drivers/clk/rockchip/clk.c +++ b/drivers/clk/rockchip/clk.c @@ -40,6 +40,7 @@ static struct clk *rockchip_clk_register_branch(const char *name, const char *const *parent_names, u8 num_parents, void __iomem *base, int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags, + u32 *mux_table, int div_offset, u8 div_shift, u8 div_width, u8 div_flags, struct clk_div_table *div_table, int gate_offset, u8 gate_shift, u8 gate_flags, unsigned long flags, @@ -62,6 +63,7 @@ static struct clk *rockchip_clk_register_branch(const char *name, mux->shift = mux_shift; mux->mask = BIT(mux_width) - 1; mux->flags = mux_flags; + mux->table = mux_table; mux->lock = lock; mux_ops = (mux_flags & CLK_MUX_READ_ONLY) ? &clk_mux_ro_ops : &clk_mux_ops; @@ -270,6 +272,8 @@ static struct clk *rockchip_clk_register_frac_branch( frac_mux->shift = child->mux_shift; frac_mux->mask = BIT(child->mux_width) - 1; frac_mux->flags = child->mux_flags; + if (child->mux_table) + frac_mux->table = child->mux_table; frac_mux->lock = lock; frac_mux->hw.init = &init; @@ -444,11 +448,21 @@ void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx, /* catch simple muxes */ switch (list->branch_type) { case branch_mux: - clk = clk_register_mux(NULL, list->name, - list->parent_names, list->num_parents, - flags, ctx->reg_base + list->muxdiv_offset, - list->mux_shift, list->mux_width, - list->mux_flags, &ctx->lock); + if (list->mux_table) + clk = clk_register_mux_table(NULL, list->name, + list->parent_names, list->num_parents, + flags, + ctx->reg_base + list->muxdiv_offset, + list->mux_shift, list->mux_width, + list->mux_flags, list->mux_table, + &ctx->lock); + else + clk = clk_register_mux(NULL, list->name, + list->parent_names, list->num_parents, + flags, + ctx->reg_base + list->muxdiv_offset, + list->mux_shift, list->mux_width, + list->mux_flags, &ctx->lock); break; case branch_muxgrf: clk = rockchip_clk_register_muxgrf(list->name, @@ -506,7 +520,8 @@ void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx, ctx->reg_base, list->muxdiv_offset, list->mux_shift, list->mux_width, list->mux_flags, - list->div_offset, list->div_shift, list->div_width, + list->mux_table, list->div_offset, + list->div_shift, list->div_width, list->div_flags, list->div_table, list->gate_offset, list->gate_shift, list->gate_flags, flags, &ctx->lock); diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index 7aa45cc70287..93937fb1d368 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -448,6 +448,7 @@ struct rockchip_clk_branch { u8 mux_shift; u8 mux_width; u8 mux_flags; + u32 *mux_table; int div_offset; u8 div_shift; u8 div_width; @@ -680,6 +681,22 @@ struct rockchip_clk_branch { .gate_offset = -1, \ } +#define MUXTBL(_id, cname, pnames, f, o, s, w, mf, mt) \ + { \ + .id = _id, \ + .branch_type = branch_mux, \ + .name = cname, \ + .parent_names = pnames, \ + .num_parents = ARRAY_SIZE(pnames), \ + .flags = f, \ + .muxdiv_offset = o, \ + .mux_shift = s, \ + .mux_width = w, \ + .mux_flags = mf, \ + .gate_offset = -1, \ + .mux_table = mt, \ + } + #define MUXGRF(_id, cname, pnames, f, o, s, w, mf) \ { \ .id = _id, \