Message ID | 20220815013039.474970-8-peng.fan@oss.nxp.com (mailing list archive) |
---|---|
State | Awaiting Upstream, archived |
Headers | show |
Series | clk: imx93: new gate API and composite update | expand |
On 22-08-15 09:30:38, Peng Fan (OSS) wrote: > From: Peng Fan <peng.fan@nxp.com> > > The clk tree should be as: > bus_aon_root------>\ /--->MU1_B IP > -->MU_B gate--> > bus_wakeup_root--->/ \--->MU2_B IP > > bus_aon_root------>\ /--->MU1_A IP > -->MU_A gate--> > bus_wakeup_root--->/ \--->MU2_A IP > > So need use shared count gate. And linux use MU_B, > so set MU_A clk as CLK_IGNORE_UNUSED. > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > Reviewed-by: Ye Li <ye.li@nxp.com> > Reviewed-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> > --- > drivers/clk/imx/clk-imx93.c | 8 ++++++-- > 1 file changed, 6 insertions(+), 2 deletions(-) > > diff --git a/drivers/clk/imx/clk-imx93.c b/drivers/clk/imx/clk-imx93.c > index 73d30a2e64b0..4008ab075dfe 100644 > --- a/drivers/clk/imx/clk-imx93.c > +++ b/drivers/clk/imx/clk-imx93.c > @@ -28,6 +28,8 @@ enum clk_sel { > MAX_SEL > }; > > +static u32 share_count_mub; > + > static const char *parent_names[MAX_SEL][4] = { > {"osc_24m", "sys_pll_pfd0_div2", "sys_pll_pfd1_div2", "video_pll"}, > {"osc_24m", "sys_pll_pfd0_div2", "sys_pll_pfd1_div2", "sys_pll_pfd2_div2"}, > @@ -159,8 +161,10 @@ static const struct imx93_clk_ccgr { > { IMX93_CLK_WDOG5_GATE, "wdog5", "osc_24m", 0x8400, }, > { IMX93_CLK_SEMA1_GATE, "sema1", "bus_aon_root", 0x8440, }, > { IMX93_CLK_SEMA2_GATE, "sema2", "bus_wakeup_root", 0x8480, }, > - { IMX93_CLK_MU_A_GATE, "mu_a", "bus_aon_root", 0x84c0, }, > - { IMX93_CLK_MU_B_GATE, "mu_b", "bus_aon_root", 0x8500, }, > + { IMX93_CLK_MU1_A_GATE, "mu1_a", "bus_aon_root", 0x84c0, CLK_IGNORE_UNUSED }, > + { IMX93_CLK_MU2_A_GATE, "mu2_a", "bus_wakeup_root", 0x84c0, CLK_IGNORE_UNUSED }, > + { IMX93_CLK_MU1_B_GATE, "mu1_b", "bus_aon_root", 0x8500, 0, &share_count_mub }, > + { IMX93_CLK_MU2_B_GATE, "mu2_b", "bus_wakeup_root", 0x8500, 0, &share_count_mub }, > { IMX93_CLK_EDMA1_GATE, "edma1", "m33_root", 0x8540, }, > { IMX93_CLK_EDMA2_GATE, "edma2", "wakeup_axi_root", 0x8580, }, > { IMX93_CLK_FLEXSPI1_GATE, "flexspi", "flexspi_root", 0x8640, }, > -- > 2.37.1 >
diff --git a/drivers/clk/imx/clk-imx93.c b/drivers/clk/imx/clk-imx93.c index 73d30a2e64b0..4008ab075dfe 100644 --- a/drivers/clk/imx/clk-imx93.c +++ b/drivers/clk/imx/clk-imx93.c @@ -28,6 +28,8 @@ enum clk_sel { MAX_SEL }; +static u32 share_count_mub; + static const char *parent_names[MAX_SEL][4] = { {"osc_24m", "sys_pll_pfd0_div2", "sys_pll_pfd1_div2", "video_pll"}, {"osc_24m", "sys_pll_pfd0_div2", "sys_pll_pfd1_div2", "sys_pll_pfd2_div2"}, @@ -159,8 +161,10 @@ static const struct imx93_clk_ccgr { { IMX93_CLK_WDOG5_GATE, "wdog5", "osc_24m", 0x8400, }, { IMX93_CLK_SEMA1_GATE, "sema1", "bus_aon_root", 0x8440, }, { IMX93_CLK_SEMA2_GATE, "sema2", "bus_wakeup_root", 0x8480, }, - { IMX93_CLK_MU_A_GATE, "mu_a", "bus_aon_root", 0x84c0, }, - { IMX93_CLK_MU_B_GATE, "mu_b", "bus_aon_root", 0x8500, }, + { IMX93_CLK_MU1_A_GATE, "mu1_a", "bus_aon_root", 0x84c0, CLK_IGNORE_UNUSED }, + { IMX93_CLK_MU2_A_GATE, "mu2_a", "bus_wakeup_root", 0x84c0, CLK_IGNORE_UNUSED }, + { IMX93_CLK_MU1_B_GATE, "mu1_b", "bus_aon_root", 0x8500, 0, &share_count_mub }, + { IMX93_CLK_MU2_B_GATE, "mu2_b", "bus_wakeup_root", 0x8500, 0, &share_count_mub }, { IMX93_CLK_EDMA1_GATE, "edma1", "m33_root", 0x8540, }, { IMX93_CLK_EDMA2_GATE, "edma2", "wakeup_axi_root", 0x8580, }, { IMX93_CLK_FLEXSPI1_GATE, "flexspi", "flexspi_root", 0x8640, },