| Message ID | 20220830125249.2373416-4-conor.dooley@microchip.com (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Headers | show |
| Series | PolarFire SoC reset controller & clock cleanups | expand |
On 30.08.2022 15:52, Conor Dooley wrote: > Add support for the resets on Microchip's PolarFire SoC (MPFS). > Reset control is a single register, wedged in between registers for > clock control. To fit with existed DT etc, the reset controller is > created using the aux device framework & set up in the clock driver. > > Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> > Acked-by: Philipp Zabel <p.zabel@pengutronix.de> > Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com> > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > drivers/reset/Kconfig | 7 ++ > drivers/reset/Makefile | 2 +- > drivers/reset/reset-mpfs.c | 157 +++++++++++++++++++++++++++++++++++++ > 3 files changed, 165 insertions(+), 1 deletion(-) > create mode 100644 drivers/reset/reset-mpfs.c > > diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig > index 806773e88832..85f7abde3766 100644 > --- a/drivers/reset/Kconfig > +++ b/drivers/reset/Kconfig > @@ -152,6 +152,13 @@ config RESET_PISTACHIO > help > This enables the reset driver for ImgTec Pistachio SoCs. > > +config RESET_POLARFIRE_SOC > + bool "Microchip PolarFire SoC (MPFS) Reset Driver" > + depends on AUXILIARY_BUS && MCHP_CLK_MPFS > + default MCHP_CLK_MPFS > + help > + This driver supports peripheral reset for the Microchip PolarFire SoC > + > config RESET_QCOM_AOSS > tristate "Qcom AOSS Reset Driver" > depends on ARCH_QCOM || COMPILE_TEST > diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile > index cd5cf8e7c6a7..3e7e5fd633a8 100644 > --- a/drivers/reset/Makefile > +++ b/drivers/reset/Makefile > @@ -22,6 +22,7 @@ obj-$(CONFIG_RESET_MESON_AUDIO_ARB) += reset-meson-audio-arb.o > obj-$(CONFIG_RESET_NPCM) += reset-npcm.o > obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o > obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o > +obj-$(CONFIG_RESET_POLARFIRE_SOC) += reset-mpfs.o > obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o > obj-$(CONFIG_RESET_QCOM_PDC) += reset-qcom-pdc.o > obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o > @@ -40,4 +41,3 @@ obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o > obj-$(CONFIG_RESET_UNIPHIER_GLUE) += reset-uniphier-glue.o > obj-$(CONFIG_RESET_ZYNQ) += reset-zynq.o > obj-$(CONFIG_ARCH_ZYNQMP) += reset-zynqmp.o > - > diff --git a/drivers/reset/reset-mpfs.c b/drivers/reset/reset-mpfs.c > new file mode 100644 > index 000000000000..1580d1b68d61 > --- /dev/null > +++ b/drivers/reset/reset-mpfs.c > @@ -0,0 +1,157 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * PolarFire SoC (MPFS) Peripheral Clock Reset Controller > + * > + * Author: Conor Dooley <conor.dooley@microchip.com> > + * Copyright (c) 2022 Microchip Technology Inc. and its subsidiaries. > + * > + */ > +#include <linux/auxiliary_bus.h> > +#include <linux/delay.h> > +#include <linux/module.h> > +#include <linux/platform_device.h> > +#include <linux/reset-controller.h> > +#include <dt-bindings/clock/microchip,mpfs-clock.h> > +#include <soc/microchip/mpfs.h> > + > +/* > + * The ENVM reset is the lowest bit in the register & I am using the CLK_FOO > + * defines in the dt to make things easier to configure - so this is accounting > + * for the offset of 3 there. > + */ > +#define MPFS_PERIPH_OFFSET CLK_ENVM > +#define MPFS_NUM_RESETS 30u > +#define MPFS_SLEEP_MIN_US 100 > +#define MPFS_SLEEP_MAX_US 200 > + > +/* block concurrent access to the soft reset register */ > +static DEFINE_SPINLOCK(mpfs_reset_lock); > + > +/* > + * Peripheral clock resets > + */ > + > +static int mpfs_assert(struct reset_controller_dev *rcdev, unsigned long id) > +{ > + unsigned long flags; > + u32 reg; > + > + spin_lock_irqsave(&mpfs_reset_lock, flags); > + > + reg = mpfs_reset_read(rcdev->dev); > + reg |= BIT(id); > + mpfs_reset_write(rcdev->dev, reg); > + > + spin_unlock_irqrestore(&mpfs_reset_lock, flags); > + > + return 0; > +} > + > +static int mpfs_deassert(struct reset_controller_dev *rcdev, unsigned long id) > +{ > + unsigned long flags; > + u32 reg, val; Using either reg or val in this function should be enough. Other than this: Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> > + > + spin_lock_irqsave(&mpfs_reset_lock, flags); > + > + reg = mpfs_reset_read(rcdev->dev); > + val = reg & ~BIT(id); > + mpfs_reset_write(rcdev->dev, val); > + > + spin_unlock_irqrestore(&mpfs_reset_lock, flags); > + > + return 0; > +} > + > +static int mpfs_status(struct reset_controller_dev *rcdev, unsigned long id) > +{ > + u32 reg = mpfs_reset_read(rcdev->dev); > + > + /* > + * It is safe to return here as MPFS_NUM_RESETS makes sure the sign bit > + * is never hit. > + */ > + return (reg & BIT(id)); > +} > + > +static int mpfs_reset(struct reset_controller_dev *rcdev, unsigned long id) > +{ > + mpfs_assert(rcdev, id); > + > + usleep_range(MPFS_SLEEP_MIN_US, MPFS_SLEEP_MAX_US); > + > + mpfs_deassert(rcdev, id); > + > + return 0; > +} > + > +static const struct reset_control_ops mpfs_reset_ops = { > + .reset = mpfs_reset, > + .assert = mpfs_assert, > + .deassert = mpfs_deassert, > + .status = mpfs_status, > +}; > + > +static int mpfs_reset_xlate(struct reset_controller_dev *rcdev, > + const struct of_phandle_args *reset_spec) > +{ > + unsigned int index = reset_spec->args[0]; > + > + /* > + * CLK_RESERVED does not map to a clock, but it does map to a reset, > + * so it has to be accounted for here. It is the reset for the fabric, > + * so if this reset gets called - do not reset it. > + */ > + if (index == CLK_RESERVED) { > + dev_err(rcdev->dev, "Resetting the fabric is not supported\n"); > + return -EINVAL; > + } > + > + if (index < MPFS_PERIPH_OFFSET || index >= (MPFS_PERIPH_OFFSET + rcdev->nr_resets)) { > + dev_err(rcdev->dev, "Invalid reset index %u\n", index); > + return -EINVAL; > + } > + > + return index - MPFS_PERIPH_OFFSET; > +} > + > +static int mpfs_reset_probe(struct auxiliary_device *adev, > + const struct auxiliary_device_id *id) > +{ > + struct device *dev = &adev->dev; > + struct reset_controller_dev *rcdev; > + > + rcdev = devm_kzalloc(dev, sizeof(*rcdev), GFP_KERNEL); > + if (!rcdev) > + return -ENOMEM; > + > + rcdev->dev = dev; > + rcdev->dev->parent = dev->parent; > + rcdev->ops = &mpfs_reset_ops; > + rcdev->of_node = dev->parent->of_node; > + rcdev->of_reset_n_cells = 1; > + rcdev->of_xlate = mpfs_reset_xlate; > + rcdev->nr_resets = MPFS_NUM_RESETS; > + > + return devm_reset_controller_register(dev, rcdev); > +} > + > +static const struct auxiliary_device_id mpfs_reset_ids[] = { > + { > + .name = "clk_mpfs.reset-mpfs", > + }, > + { } > +}; > +MODULE_DEVICE_TABLE(auxiliary, mpfs_reset_ids); > + > +static struct auxiliary_driver mpfs_reset_driver = { > + .probe = mpfs_reset_probe, > + .id_table = mpfs_reset_ids, > +}; > + > +module_auxiliary_driver(mpfs_reset_driver); > + > +MODULE_DESCRIPTION("Microchip PolarFire SoC Reset Driver"); > +MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>"); > +MODULE_LICENSE("GPL"); > +MODULE_IMPORT_NS(MCHP_CLK_MPFS);
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 806773e88832..85f7abde3766 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -152,6 +152,13 @@ config RESET_PISTACHIO help This enables the reset driver for ImgTec Pistachio SoCs. +config RESET_POLARFIRE_SOC + bool "Microchip PolarFire SoC (MPFS) Reset Driver" + depends on AUXILIARY_BUS && MCHP_CLK_MPFS + default MCHP_CLK_MPFS + help + This driver supports peripheral reset for the Microchip PolarFire SoC + config RESET_QCOM_AOSS tristate "Qcom AOSS Reset Driver" depends on ARCH_QCOM || COMPILE_TEST diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index cd5cf8e7c6a7..3e7e5fd633a8 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -22,6 +22,7 @@ obj-$(CONFIG_RESET_MESON_AUDIO_ARB) += reset-meson-audio-arb.o obj-$(CONFIG_RESET_NPCM) += reset-npcm.o obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o +obj-$(CONFIG_RESET_POLARFIRE_SOC) += reset-mpfs.o obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o obj-$(CONFIG_RESET_QCOM_PDC) += reset-qcom-pdc.o obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o @@ -40,4 +41,3 @@ obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o obj-$(CONFIG_RESET_UNIPHIER_GLUE) += reset-uniphier-glue.o obj-$(CONFIG_RESET_ZYNQ) += reset-zynq.o obj-$(CONFIG_ARCH_ZYNQMP) += reset-zynqmp.o - diff --git a/drivers/reset/reset-mpfs.c b/drivers/reset/reset-mpfs.c new file mode 100644 index 000000000000..1580d1b68d61 --- /dev/null +++ b/drivers/reset/reset-mpfs.c @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * PolarFire SoC (MPFS) Peripheral Clock Reset Controller + * + * Author: Conor Dooley <conor.dooley@microchip.com> + * Copyright (c) 2022 Microchip Technology Inc. and its subsidiaries. + * + */ +#include <linux/auxiliary_bus.h> +#include <linux/delay.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/reset-controller.h> +#include <dt-bindings/clock/microchip,mpfs-clock.h> +#include <soc/microchip/mpfs.h> + +/* + * The ENVM reset is the lowest bit in the register & I am using the CLK_FOO + * defines in the dt to make things easier to configure - so this is accounting + * for the offset of 3 there. + */ +#define MPFS_PERIPH_OFFSET CLK_ENVM +#define MPFS_NUM_RESETS 30u +#define MPFS_SLEEP_MIN_US 100 +#define MPFS_SLEEP_MAX_US 200 + +/* block concurrent access to the soft reset register */ +static DEFINE_SPINLOCK(mpfs_reset_lock); + +/* + * Peripheral clock resets + */ + +static int mpfs_assert(struct reset_controller_dev *rcdev, unsigned long id) +{ + unsigned long flags; + u32 reg; + + spin_lock_irqsave(&mpfs_reset_lock, flags); + + reg = mpfs_reset_read(rcdev->dev); + reg |= BIT(id); + mpfs_reset_write(rcdev->dev, reg); + + spin_unlock_irqrestore(&mpfs_reset_lock, flags); + + return 0; +} + +static int mpfs_deassert(struct reset_controller_dev *rcdev, unsigned long id) +{ + unsigned long flags; + u32 reg, val; + + spin_lock_irqsave(&mpfs_reset_lock, flags); + + reg = mpfs_reset_read(rcdev->dev); + val = reg & ~BIT(id); + mpfs_reset_write(rcdev->dev, val); + + spin_unlock_irqrestore(&mpfs_reset_lock, flags); + + return 0; +} + +static int mpfs_status(struct reset_controller_dev *rcdev, unsigned long id) +{ + u32 reg = mpfs_reset_read(rcdev->dev); + + /* + * It is safe to return here as MPFS_NUM_RESETS makes sure the sign bit + * is never hit. + */ + return (reg & BIT(id)); +} + +static int mpfs_reset(struct reset_controller_dev *rcdev, unsigned long id) +{ + mpfs_assert(rcdev, id); + + usleep_range(MPFS_SLEEP_MIN_US, MPFS_SLEEP_MAX_US); + + mpfs_deassert(rcdev, id); + + return 0; +} + +static const struct reset_control_ops mpfs_reset_ops = { + .reset = mpfs_reset, + .assert = mpfs_assert, + .deassert = mpfs_deassert, + .status = mpfs_status, +}; + +static int mpfs_reset_xlate(struct reset_controller_dev *rcdev, + const struct of_phandle_args *reset_spec) +{ + unsigned int index = reset_spec->args[0]; + + /* + * CLK_RESERVED does not map to a clock, but it does map to a reset, + * so it has to be accounted for here. It is the reset for the fabric, + * so if this reset gets called - do not reset it. + */ + if (index == CLK_RESERVED) { + dev_err(rcdev->dev, "Resetting the fabric is not supported\n"); + return -EINVAL; + } + + if (index < MPFS_PERIPH_OFFSET || index >= (MPFS_PERIPH_OFFSET + rcdev->nr_resets)) { + dev_err(rcdev->dev, "Invalid reset index %u\n", index); + return -EINVAL; + } + + return index - MPFS_PERIPH_OFFSET; +} + +static int mpfs_reset_probe(struct auxiliary_device *adev, + const struct auxiliary_device_id *id) +{ + struct device *dev = &adev->dev; + struct reset_controller_dev *rcdev; + + rcdev = devm_kzalloc(dev, sizeof(*rcdev), GFP_KERNEL); + if (!rcdev) + return -ENOMEM; + + rcdev->dev = dev; + rcdev->dev->parent = dev->parent; + rcdev->ops = &mpfs_reset_ops; + rcdev->of_node = dev->parent->of_node; + rcdev->of_reset_n_cells = 1; + rcdev->of_xlate = mpfs_reset_xlate; + rcdev->nr_resets = MPFS_NUM_RESETS; + + return devm_reset_controller_register(dev, rcdev); +} + +static const struct auxiliary_device_id mpfs_reset_ids[] = { + { + .name = "clk_mpfs.reset-mpfs", + }, + { } +}; +MODULE_DEVICE_TABLE(auxiliary, mpfs_reset_ids); + +static struct auxiliary_driver mpfs_reset_driver = { + .probe = mpfs_reset_probe, + .id_table = mpfs_reset_ids, +}; + +module_auxiliary_driver(mpfs_reset_driver); + +MODULE_DESCRIPTION("Microchip PolarFire SoC Reset Driver"); +MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>"); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS(MCHP_CLK_MPFS);