From patchwork Thu Sep 8 14:36:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12970201 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA0DDC54EE9 for ; Thu, 8 Sep 2022 14:37:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231773AbiIHOhl (ORCPT ); Thu, 8 Sep 2022 10:37:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54544 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232569AbiIHOhh (ORCPT ); Thu, 8 Sep 2022 10:37:37 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3C13DE6233; Thu, 8 Sep 2022 07:37:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1662647857; x=1694183857; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ggvgSTbI/3n106FcPTJ8++adTEBX7bnWFulBMj2Sqa4=; b=PRxkv8xQkCeZ9ax3M2Psa99MWuL7Khbj8iQ+6QaEqy0SXYI9BmQgisWv v0OYQvj92jrV2rDmE5O+C5yHl4V5PpNlBAQ6N5G1+WnZJESYP80iiR0+d AYyr3vxQpgyv1NrkJbby9sdQHROLE5Z2AUjATr7OtPg+TFMFlpOrxplMs Ej2VhkJCbM3O+IAw68SnzTz2Cj60t5hDFumvx5dGYzZrF2H+TmqPQjIG5 aTJNhoOeRa6R72BzKa7w4eL8GB4RjdPTV9P00ZIy/I43c5qHXGmQbqvn8 6m+2FQb2nQcx1HmFqx2K0jf8PpiBTkpoFxeR8W7uMuAIapVsI4ZLKjtTM A==; X-IronPort-AV: E=Sophos;i="5.93,300,1654585200"; d="scan'208";a="172970687" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 08 Sep 2022 07:37:36 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Thu, 8 Sep 2022 07:37:35 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Thu, 8 Sep 2022 07:37:32 -0700 From: Conor Dooley To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Conor Dooley , Daire McNamara , Hugh Breslin CC: Paul Walmsley , Albert Ou , Claudiu Beznea , , , , , "Krzysztof Kozlowski" Subject: [PATCH v5 3/5] dt-bindings: clk: add PolarFire SoC fabric clock ids Date: Thu, 8 Sep 2022 15:36:50 +0100 Message-ID: <20220908143651.1252601-4-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220908143651.1252601-1-conor.dooley@microchip.com> References: <20220908143651.1252601-1-conor.dooley@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Each Clock Conditioning Circuitry block contains 2 PLLs and 2 DLLs. The PLLs have 4 outputs each and the DLLs 2. Add 16 new IDs covering these clocks. For more information on the CCC hardware, see the "PolarFire SoC FPGA Clocking Resources" document at the link below. Link: https://onlinedocs.microchip.com/pr/GUID-8F0CC4C0-0317-4262-89CA-CE7773ED1931-en-US-1/index.html Acked-by: Krzysztof Kozlowski Signed-off-by: Conor Dooley --- .../dt-bindings/clock/microchip,mpfs-clock.h | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/include/dt-bindings/clock/microchip,mpfs-clock.h b/include/dt-bindings/clock/microchip,mpfs-clock.h index 4048669bf756..79775a5134ca 100644 --- a/include/dt-bindings/clock/microchip,mpfs-clock.h +++ b/include/dt-bindings/clock/microchip,mpfs-clock.h @@ -45,4 +45,27 @@ #define CLK_RTCREF 33 #define CLK_MSSPLL 34 +/* Clock Conditioning Circuitry Clock IDs */ + +#define CLK_CCC_PLL0 0 +#define CLK_CCC_PLL1 1 +#define CLK_CCC_DLL0 2 +#define CLK_CCC_DLL1 3 + +#define CLK_CCC_PLL0_OUT0 4 +#define CLK_CCC_PLL0_OUT1 5 +#define CLK_CCC_PLL0_OUT2 6 +#define CLK_CCC_PLL0_OUT3 7 + +#define CLK_CCC_PLL1_OUT0 8 +#define CLK_CCC_PLL1_OUT1 9 +#define CLK_CCC_PLL1_OUT2 10 +#define CLK_CCC_PLL1_OUT3 11 + +#define CLK_CCC_DLL0_OUT0 12 +#define CLK_CCC_DLL0_OUT1 13 + +#define CLK_CCC_DLL1_OUT0 14 +#define CLK_CCC_DLL1_OUT1 15 + #endif /* _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ */