From patchwork Fri Sep 9 12:31:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12971698 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 724B8C6FA92 for ; Fri, 9 Sep 2022 12:32:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231742AbiIIMcW (ORCPT ); Fri, 9 Sep 2022 08:32:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56388 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231545AbiIIMcP (ORCPT ); Fri, 9 Sep 2022 08:32:15 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 44C89124606; Fri, 9 Sep 2022 05:32:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1662726733; x=1694262733; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=G+WYVhgOvW4xmI5fmn7rIAM6FUhUnHezJLVWecWQzyI=; b=Ktyz8uIhDPgb9d3A0JuQHnoO8gqxIu7pv0GnpJTwgCKOc4xNRc65Pye+ e1DPL9DscXX5poVw/nn4azzlaDMEv4zfww9QPV+xgr7FV3D0ccgKm10sO MnS4V6/3AreDqKwbuTW34xdnvsCwC5ogRdxvRr2WyFMiNOF+bK9r9QmBt jME03Or1Ap8+RCGT+8K0ZpCf59yWj0mqoCXnb+5wv7zMplHLivT0StvgS LWyKxliG6a1JeiDCHkIW2QJ25Vi+MqslbCW6YgNCC6MQrfIX9nbeRTe5X EmIFG+lXLJnWlFYuLi5QPLHzhjQuUkmDlglPx5mxviBq0htUKiOGU+UUY A==; X-IronPort-AV: E=Sophos;i="5.93,303,1654585200"; d="scan'208";a="179721685" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 09 Sep 2022 05:32:13 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Fri, 9 Sep 2022 05:32:11 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Fri, 9 Sep 2022 05:32:09 -0700 From: Conor Dooley To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Conor Dooley , Daire McNamara CC: Paul Walmsley , Albert Ou , Claudiu Beznea , , , , Subject: [PATCH v5 09/14] clk: microchip: mpfs: move id & offset out of clock structs Date: Fri, 9 Sep 2022 13:31:18 +0100 Message-ID: <20220909123123.2699583-10-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220909123123.2699583-1-conor.dooley@microchip.com> References: <20220909123123.2699583-1-conor.dooley@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The id and offset are the only thing differentiating the clock structs from "regular" clock structures. On the pretext of converting to more normal structures, move the id and offset out of the clock structs and into the hw structs instead. Reviewed-by: Daire McNamara Signed-off-by: Conor Dooley Reviewed-by: Claudiu Beznea --- drivers/clk/microchip/clk-mpfs.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/drivers/clk/microchip/clk-mpfs.c b/drivers/clk/microchip/clk-mpfs.c index f40d22293539..9250fab88ebf 100644 --- a/drivers/clk/microchip/clk-mpfs.c +++ b/drivers/clk/microchip/clk-mpfs.c @@ -51,8 +51,6 @@ struct mpfs_msspll_hw_clock { struct mpfs_cfg_clock { const struct clk_div_table *table; - unsigned int id; - u32 reg_offset; u8 shift; u8 width; u8 flags; @@ -63,12 +61,13 @@ struct mpfs_cfg_hw_clock { void __iomem *sys_base; struct clk_hw hw; struct clk_init_data init; + unsigned int id; + u32 reg_offset; }; #define to_mpfs_cfg_clk(_hw) container_of(_hw, struct mpfs_cfg_hw_clock, hw) struct mpfs_periph_clock { - unsigned int id; u8 shift; }; @@ -76,6 +75,7 @@ struct mpfs_periph_hw_clock { struct mpfs_periph_clock periph; void __iomem *sys_base; struct clk_hw hw; + unsigned int id; }; #define to_mpfs_periph_clk(_hw) container_of(_hw, struct mpfs_periph_hw_clock, hw) @@ -241,7 +241,7 @@ static unsigned long mpfs_cfg_clk_recalc_rate(struct clk_hw *hw, unsigned long p void __iomem *base_addr = cfg_hw->sys_base; u32 val; - val = readl_relaxed(base_addr + cfg->reg_offset) >> cfg->shift; + val = readl_relaxed(base_addr + cfg_hw->reg_offset) >> cfg->shift; val &= clk_div_mask(cfg->width); return divider_recalc_rate(hw, prate, val, cfg->table, cfg->flags, cfg->width); @@ -270,10 +270,10 @@ static int mpfs_cfg_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned return divider_setting; spin_lock_irqsave(&mpfs_clk_lock, flags); - val = readl_relaxed(base_addr + cfg->reg_offset); + val = readl_relaxed(base_addr + cfg_hw->reg_offset); val &= ~(clk_div_mask(cfg->width) << cfg_hw->cfg.shift); val |= divider_setting << cfg->shift; - writel_relaxed(val, base_addr + cfg->reg_offset); + writel_relaxed(val, base_addr + cfg_hw->reg_offset); spin_unlock_irqrestore(&mpfs_clk_lock, flags); @@ -287,11 +287,11 @@ static const struct clk_ops mpfs_clk_cfg_ops = { }; #define CLK_CFG(_id, _name, _parent, _shift, _width, _table, _flags, _offset) { \ - .cfg.id = _id, \ + .id = _id, \ .cfg.shift = _shift, \ .cfg.width = _width, \ .cfg.table = _table, \ - .cfg.reg_offset = _offset, \ + .reg_offset = _offset, \ .cfg.flags = _flags, \ .hw.init = CLK_HW_INIT(_name, _parent, &mpfs_clk_cfg_ops, 0), \ } @@ -309,11 +309,11 @@ static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] = { CLK_CFG(CLK_AHB, "clk_ahb", "clk_msspll", 4, 2, mpfs_div_ahb_table, 0, REG_CLOCK_CONFIG_CR), { - .cfg.id = CLK_RTCREF, + .id = CLK_RTCREF, .cfg.shift = 0, .cfg.width = 12, .cfg.table = mpfs_div_rtcref_table, - .cfg.reg_offset = REG_RTC_CLOCK_CR, + .reg_offset = REG_RTC_CLOCK_CR, .cfg.flags = CLK_DIVIDER_ONE_BASED, .hw.init = CLK_HW_INIT_PARENTS_DATA("clk_rtcref", mpfs_ext_ref, &mpfs_clk_cfg_ops, 0), @@ -341,9 +341,9 @@ static int mpfs_clk_register_cfgs(struct device *dev, struct mpfs_cfg_hw_clock * ret = mpfs_clk_register_cfg(dev, cfg_hw, sys_base); if (ret) return dev_err_probe(dev, ret, "failed to register clock id: %d\n", - cfg_hw->cfg.id); + cfg_hw->id); - id = cfg_hw->cfg.id; + id = cfg_hw->id; data->hw_data.hws[id] = &cfg_hw->hw; } @@ -411,7 +411,7 @@ static const struct clk_ops mpfs_periph_clk_ops = { }; #define CLK_PERIPH(_id, _name, _parent, _shift, _flags) { \ - .periph.id = _id, \ + .id = _id, \ .periph.shift = _shift, \ .hw.init = CLK_HW_INIT_HW(_name, _parent, &mpfs_periph_clk_ops, \ _flags), \ @@ -486,9 +486,9 @@ static int mpfs_clk_register_periphs(struct device *dev, struct mpfs_periph_hw_c ret = mpfs_clk_register_periph(dev, periph_hw, sys_base); if (ret) return dev_err_probe(dev, ret, "failed to register clock id: %d\n", - periph_hw->periph.id); + periph_hw->id); - id = periph_hws[i].periph.id; + id = periph_hws[i].id; data->hw_data.hws[id] = &periph_hw->hw; }