@@ -573,9 +573,10 @@ fec_mac_address: mac-address@90 {
};
};
- anatop: anatop@30360000 {
- compatible = "fsl,imx8mm-anatop", "syscon";
+ anatop: clock-controller@30360000 {
+ compatible = "fsl,imx8mm-anatop";
reg = <0x30360000 0x10000>;
+ #clock-cells = <1>;
};
snvs: snvs@30370000 {
@@ -576,10 +576,10 @@ fec_mac_address: mac-address@90 {
};
};
- anatop: anatop@30360000 {
- compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop",
- "syscon";
+ anatop: clock-controller@30360000 {
+ compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop";
reg = <0x30360000 0x10000>;
+ #clock-cells = <1>;
};
snvs: snvs@30370000 {
@@ -441,10 +441,10 @@ eth_mac2: mac-address@96 {
};
};
- anatop: anatop@30360000 {
- compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop",
- "syscon";
+ anatop: clock-controller@30360000 {
+ compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop";
reg = <0x30360000 0x10000>;
+ #clock-cells = <1>;
};
snvs: snvs@30370000 {
@@ -605,10 +605,11 @@ fec_mac_address: mac-address@90 {
};
};
- anatop: syscon@30360000 {
- compatible = "fsl,imx8mq-anatop", "syscon";
+ anatop: clock-controller@30360000 {
+ compatible = "fsl,imx8mq-anatop";
reg = <0x30360000 0x10000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ #clock-cells = <1>;
};
snvs: snvs@30370000 {