diff mbox series

[v3,01/10] arm64: dts: mt8183: Fix Mali GPU clock

Message ID 20220927101128.44758-2-angelogioacchino.delregno@collabora.com (mailing list archive)
State Not Applicable, archived
Headers show
Series MediaTek SoC safe clock muxing and GPU clocks | expand

Commit Message

AngeloGioacchino Del Regno Sept. 27, 2022, 10:11 a.m. UTC 
From: Chen-Yu Tsai <wenst@chromium.org>

The actual clock feeding into the Mali GPU on the MT8183 is from the
clock gate in the MFGCFG block, not CLK_TOP_MFGPLL_CK from the TOPCKGEN
block, which itself is simply a pass-through placeholder for the MFGPLL
in the APMIXEDSYS block.

Fix the hardware description with the correct clock reference.

Fixes: a8168cebf1bc ("arm64: dts: mt8183: Add node for the Mali GPU")
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8183.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Nícolas F. R. A. Prado Dec. 6, 2022, 6:30 p.m. UTC | #1 
On Tue, Sep 27, 2022 at 12:11:19PM +0200, AngeloGioacchino Del Regno wrote:
> From: Chen-Yu Tsai <wenst@chromium.org>
> 
> The actual clock feeding into the Mali GPU on the MT8183 is from the
> clock gate in the MFGCFG block, not CLK_TOP_MFGPLL_CK from the TOPCKGEN
> block, which itself is simply a pass-through placeholder for the MFGPLL
> in the APMIXEDSYS block.
> 
> Fix the hardware description with the correct clock reference.
> 
> Fixes: a8168cebf1bc ("arm64: dts: mt8183: Add node for the Mali GPU")
> Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Hi,

it seems that while all other patches on this series were applied by Chen-Yu
through the clk tree, this commit never made it to the mediatek tree.

As a result, MT8183-based machines (or at least mt8183-kukui-jacuzzi, where I
tested on) currently hang during boot not only on next, but also on mainline,
v6.1-rc8. With this commit applied I've confirmed that the machine boots fine
again.

Matthias, could you please apply this commit and make sure it makes its way to
v6.1? Given the Fixes tag it should eventually make its way there anyway, but if
still possible would be good to have it fixed right from v6.1.

Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

Thanks,
Nícolas

> ---
>  arch/arm64/boot/dts/mediatek/mt8183.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> index a70b669c49ba..402136bfd535 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> @@ -1678,7 +1678,7 @@ gpu: gpu@13040000 {
>  				<GIC_SPI 278 IRQ_TYPE_LEVEL_LOW>;
>  			interrupt-names = "job", "mmu", "gpu";
>  
> -			clocks = <&topckgen CLK_TOP_MFGPLL_CK>;
> +			clocks = <&mfgcfg CLK_MFG_BG3D>;
>  
>  			power-domains =
>  				<&spm MT8183_POWER_DOMAIN_MFG_CORE0>,
> -- 
> 2.37.2
> 
> 
>
Matthias Brugger Dec. 16, 2022, 10:46 a.m. UTC | #2 
On 06/12/2022 19:30, Nícolas F. R. A. Prado wrote:
> On Tue, Sep 27, 2022 at 12:11:19PM +0200, AngeloGioacchino Del Regno wrote:
>> From: Chen-Yu Tsai <wenst@chromium.org>
>>
>> The actual clock feeding into the Mali GPU on the MT8183 is from the
>> clock gate in the MFGCFG block, not CLK_TOP_MFGPLL_CK from the TOPCKGEN
>> block, which itself is simply a pass-through placeholder for the MFGPLL
>> in the APMIXEDSYS block.
>>
>> Fix the hardware description with the correct clock reference.
>>
>> Fixes: a8168cebf1bc ("arm64: dts: mt8183: Add node for the Mali GPU")
>> Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
>> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> 
> Hi,
> 
> it seems that while all other patches on this series were applied by Chen-Yu
> through the clk tree, this commit never made it to the mediatek tree.
> 
> As a result, MT8183-based machines (or at least mt8183-kukui-jacuzzi, where I
> tested on) currently hang during boot not only on next, but also on mainline,
> v6.1-rc8. With this commit applied I've confirmed that the machine boots fine
> again.
> 
> Matthias, could you please apply this commit and make sure it makes its way to
> v6.1? Given the Fixes tag it should eventually make its way there anyway, but if
> still possible would be good to have it fixed right from v6.1.
> 
> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

Applied now.

Sorry for the late reply.
Matthias

> 
> Thanks,
> Nícolas
> 
>> ---
>>   arch/arm64/boot/dts/mediatek/mt8183.dtsi | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>> index a70b669c49ba..402136bfd535 100644
>> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>> @@ -1678,7 +1678,7 @@ gpu: gpu@13040000 {
>>   				<GIC_SPI 278 IRQ_TYPE_LEVEL_LOW>;
>>   			interrupt-names = "job", "mmu", "gpu";
>>   
>> -			clocks = <&topckgen CLK_TOP_MFGPLL_CK>;
>> +			clocks = <&mfgcfg CLK_MFG_BG3D>;
>>   
>>   			power-domains =
>>   				<&spm MT8183_POWER_DOMAIN_MFG_CORE0>,
>> -- 
>> 2.37.2
>>
>>
>>
Matthias Brugger Dec. 16, 2022, 11:23 a.m. UTC | #3 
On 27/09/2022 12:11, AngeloGioacchino Del Regno wrote:
> From: Chen-Yu Tsai <wenst@chromium.org>
> 
> The actual clock feeding into the Mali GPU on the MT8183 is from the
> clock gate in the MFGCFG block, not CLK_TOP_MFGPLL_CK from the TOPCKGEN
> block, which itself is simply a pass-through placeholder for the MFGPLL
> in the APMIXEDSYS block.
> 
> Fix the hardware description with the correct clock reference.
> 
> Fixes: a8168cebf1bc ("arm64: dts: mt8183: Add node for the Mali GPU")
> Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Both patches applied, thanks!

> ---
>   arch/arm64/boot/dts/mediatek/mt8183.dtsi | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> index a70b669c49ba..402136bfd535 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> @@ -1678,7 +1678,7 @@ gpu: gpu@13040000 {
>   				<GIC_SPI 278 IRQ_TYPE_LEVEL_LOW>;
>   			interrupt-names = "job", "mmu", "gpu";
>   
> -			clocks = <&topckgen CLK_TOP_MFGPLL_CK>;
> +			clocks = <&mfgcfg CLK_MFG_BG3D>;
>   
>   			power-domains =
>   				<&spm MT8183_POWER_DOMAIN_MFG_CORE0>,
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index a70b669c49ba..402136bfd535 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -1678,7 +1678,7 @@  gpu: gpu@13040000 {
 				<GIC_SPI 278 IRQ_TYPE_LEVEL_LOW>;
 			interrupt-names = "job", "mmu", "gpu";
 
-			clocks = <&topckgen CLK_TOP_MFGPLL_CK>;
+			clocks = <&mfgcfg CLK_MFG_BG3D>;
 
 			power-domains =
 				<&spm MT8183_POWER_DOMAIN_MFG_CORE0>,