From patchwork Fri Sep 30 07:38:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hal Feng X-Patchwork-Id: 12995026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6506CC4332F for ; Fri, 30 Sep 2022 07:41:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231220AbiI3HlN (ORCPT ); Fri, 30 Sep 2022 03:41:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35338 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229780AbiI3HlJ (ORCPT ); Fri, 30 Sep 2022 03:41:09 -0400 Received: from bg4.exmail.qq.com (bg4.exmail.qq.com [43.155.67.158]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4F9CB1032E2; Fri, 30 Sep 2022 00:41:04 -0700 (PDT) X-QQ-mid: bizesmtp64t1664523533tfs8q1ju Received: from localhost.localdomain ( [113.72.146.201]) by bizesmtp.qq.com (ESMTP) with id ; Fri, 30 Sep 2022 15:38:51 +0800 (CST) X-QQ-SSF: 01000000000000305000000A0000000 X-QQ-FEAT: k8Irs33ik7vaMfpcnYWCuh3AHagj5K0mh271a0EEiwEVFUL7rSfkc84AaA7xx FgVUPVwT/bikpDFHdgNhxbLCszQfXzRjkBFWClSgjKwYqaFgUEc+6KJehrpi+KbWQOhgJ9D hfDzq8j5+S8X0DeV5We0ny9HZyOuhv2nWBulRgG4Ojbch1Ef9mB8WUs8B/SJI1uvt6ci5C4 C0iwQU7s+ajU5SVtZpib1WaES9ba4RsGW63jrR5XOO6AVPlpWIqwlrdTdq6Y/GuNytIrnE4 aGKYYRTzuqP7U/k12ijT6UMYg9Qr18UwtUWSikyluGgcZG7QyFmcymmM7/7kfVuQSYPdAMR cPQ7PxQIDV6a1ZmNDoHMahsZ6B4QbodHR6LIR2uftqy/MW5Bgf+VvQRNTs7+T7CvQIa1U+g G+A3mq2f1JSSsGDzG8X2+w== X-QQ-GoodBg: 0 From: Hal Feng To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org Cc: Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Thomas Gleixner , Marc Zyngier , Philipp Zabel , Stephen Boyd , Michael Turquette , Linus Walleij , Emil Renner Berthing , Hal Feng , linux-kernel@vger.kernel.org Subject: [PATCH v1 25/30] dt-bindings: pinctrl: Add StarFive JH7110 pinctrl bindings Date: Fri, 30 Sep 2022 15:38:45 +0800 Message-Id: <20220930073845.6309-1-hal.feng@linux.starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220929143225.17907-1-hal.feng@linux.starfivetech.com> References: <20220929143225.17907-1-hal.feng@linux.starfivetech.com> X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:linux.starfivetech.com:qybglogicsvr:qybglogicsvr2 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org From: Jianlong Huang Add pinctrl bindings for StarFive JH7110 SoC. Signed-off-by: Jianlong Huang Signed-off-by: Hal Feng --- .../pinctrl/starfive,jh7110-pinctrl.yaml | 202 ++++++++++++++++++ 1 file changed, 202 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jh7110-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-pinctrl.yaml new file mode 100644 index 000000000000..482012ad8a14 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-pinctrl.yaml @@ -0,0 +1,202 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/starfive,jh7110-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 Pin Controller Device Tree Bindings + +description: | + Bindings for the JH7110 RISC-V SoC from StarFive Technology Ltd. + +maintainers: + - Jianlong Huang + +properties: + compatible: + enum: + - starfive,jh7110-sys-pinctrl + - starfive,jh7110-aon-pinctrl + + reg: + minItems: 2 + maxItems: 2 + + reg-names: + items: + - const: control + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + "#gpio-cells": + const: 2 + + interrupts: + maxItems: 1 + description: The GPIO parent interrupt. + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + ngpios: + enum: + - 64 + - 4 + +required: + - compatible + - reg + - reg-names + - clocks + - "#gpio-cells" + - interrupts + - interrupt-controller + - "#interrupt-cells" + +patternProperties: + '-[0-9]+$': + type: object + patternProperties: + '-pins$': + type: object + description: | + A pinctrl node should contain at least one subnode representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to + muxer configuration, system signal configuration, pin groups for + vin/vout module, pin voltage, mux functions for output, mux functions + for output enable, mux functions for input. + + properties: + starfive,pins: + description: | + The list of pin identifiers that properties in the node apply to. + This should be set using the PAD_GPIOX macros. + This has to be specified. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 63 + + starfive,pinmux: + description: | + The list of GPIOs and their mux functions that properties in the + node apply to. This should be set using the PAD_GPIOX_FUNC_SEL + macro with its value. + This is optional for some pins. + The value of PAD_GPIOX_FUNC_SEL macro can selects: + 0: GPIOX mux function 0, + 1: GPIOX mux function 1, + 2: GPIOX mux function 2. + + starfive,pin-ioconfig: + description: | + This is used to configure the core settings of system signals. + The combination of GPIO_IE or GPIO_DS or GPIO_PU or GPIO_PD or + GPIO_SLEW or GPIO_SMT or GPIO_POS. + $ref: /schemas/types.yaml#/definitions/uint32 + + starfive,padmux: + description: | + The padmux is for vin/vout module to select pin groups. + 0: vout will be set at pins from PAD_GPIO7 to PAD_GPIO34, + when PAD_GPIOX_FUNC_SEL is set as 1. + vin will be set at pins from PAD_GPIO6 to PAD_GPIO20. + when PAD_GPIOX_FUNC_SEL is set as 2. + 1: vout will be set at pins from PAD_GPIO36 to PAD_GPIO63, + when PAD_GPIOX_FUNC_SEL is set as 1. + vin will be set at pins from PAD_GPIO21 to PAD_GPIO35. + when PAD_GPIOX_FUNC_SEL is set as 2. + 2: vin will be set at pins from PAD_GPIO36 to PAD_GPIO50, + when PAD_GPIOX_FUNC_SEL is set as 2 + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2] + + starfive,pin-syscon: + description: | + This is used to set pin voltage, + 0: 3.3V, 1: 2.5V, 2: 1.8V. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2] + + starfive,pin-gpio-dout: + description: | + This is used to set their mux functions for output. + This should be set using the GPO_XXX macro, + such as GPO_LOW, GPO_UART0_SOUT. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 107 + + starfive,pin-gpio-doen: + description: | + This is used to set their mux functions for output enable. + This should be set using the OEN_XXX macro, + such as OEN_LOW, OEN_I2C0_IC_CLK_OE. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 49 + + starfive,pin-gpio-din: + description: | + This is used to set their mux functions for input. + This should be set using the GPI_XXX macro, + such as GPI_CAN0_CTRL_RXD, GPI_I2C0_IC_CLK_IN_A. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 90 + + additionalProperties: false + + additionalProperties: false + +additionalProperties: false + +examples: + - | + #include + #include + #include + + gpio: gpio@13040000 { + compatible = "starfive,jh7110-sys-pinctrl"; + reg = <0x0 0x13040000 0x0 0x10000>; + reg-names = "control"; + clocks = <&clkgen JH7110_SYS_IOMUX_PCLK>; + resets = <&rstgen RSTN_U0_SYS_IOMUX_PRESETN>; + interrupts = <86>; + interrupt-controller; + #gpio-cells = <2>; + ngpios = <64>; + status = "okay"; + + uart0_pins: uart0-pins { + uart0-pins-tx { + starfive,pins = ; + starfive,pin-ioconfig = ; + starfive,pin-gpio-dout = ; + starfive,pin-gpio-doen = ; + }; + + uart0-pins-rx { + starfive,pins = ; + starfive,pinmux = ; + starfive,pin-ioconfig = ; + starfive,pin-gpio-doen = ; + starfive,pin-gpio-din = ; + }; + }; + }; + + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; + }; + +...