diff mbox series

[v2,2/2] clk: renesas: r9a07g044: Add CRU_SYSCLK and CRU_VCLK to no PM list

Message ID 20221026014227.162121-3-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive)
State Changes Requested, archived
Headers show
Series clk: renesas: RZ/G2L: Add support for no PM clocks | expand

Commit Message

Lad, Prabhakar Oct. 26, 2022, 1:42 a.m. UTC 
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

CRU_SYSCLK and CRU_VCLK clocks need to be turned ON/OFF in particular
sequence for the CRU block hence add these clocks to
r9a07g044_no_pm_mod_clks[] array.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2
* Dropped usage of DEF_NO_PM() macro
* Added CRU_SYSCLK and CRU_VCLK to no PM list
* Updated commit message

RFC->v1
* No change
---
 drivers/clk/renesas/r9a07g044-cpg.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

Comments

Geert Uytterhoeven Oct. 26, 2022, 7:58 a.m. UTC | #1 
Hi Prabhakar,

On Wed, Oct 26, 2022 at 3:42 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> CRU_SYSCLK and CRU_VCLK clocks need to be turned ON/OFF in particular
> sequence for the CRU block hence add these clocks to
> r9a07g044_no_pm_mod_clks[] array.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v1->v2
> * Dropped usage of DEF_NO_PM() macro
> * Added CRU_SYSCLK and CRU_VCLK to no PM list
> * Updated commit message

Thanks for the update!

> --- a/drivers/clk/renesas/r9a07g044-cpg.c
> +++ b/drivers/clk/renesas/r9a07g044-cpg.c
> @@ -412,6 +412,11 @@ static const unsigned int r9a07g044_crit_mod_clks[] __initconst = {
>         MOD_CLK_BASE + R9A07G044_DMAC_ACLK,
>  };
>
> +static const unsigned int r9a07g044_no_pm_mod_clks[] __initconst = {

This cannot be __initconst, so please drop this keyword.

> +       MOD_CLK_BASE + R9A07G044_CRU_SYSCLK,
> +       MOD_CLK_BASE + R9A07G044_CRU_VCLK,
> +};

I believe I haven't seen patches yet to add support for these clocks?
Perhaps these can be combined?

Thanks!

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
Lad, Prabhakar Oct. 26, 2022, 9:02 a.m. UTC | #2 
Hi Geert,

THank you for the review.

On Wed, Oct 26, 2022 at 8:58 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Wed, Oct 26, 2022 at 3:42 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > CRU_SYSCLK and CRU_VCLK clocks need to be turned ON/OFF in particular
> > sequence for the CRU block hence add these clocks to
> > r9a07g044_no_pm_mod_clks[] array.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > v1->v2
> > * Dropped usage of DEF_NO_PM() macro
> > * Added CRU_SYSCLK and CRU_VCLK to no PM list
> > * Updated commit message
>
> Thanks for the update!
>
> > --- a/drivers/clk/renesas/r9a07g044-cpg.c
> > +++ b/drivers/clk/renesas/r9a07g044-cpg.c
> > @@ -412,6 +412,11 @@ static const unsigned int r9a07g044_crit_mod_clks[] __initconst = {
> >         MOD_CLK_BASE + R9A07G044_DMAC_ACLK,
> >  };
> >
> > +static const unsigned int r9a07g044_no_pm_mod_clks[] __initconst = {
>
> This cannot be __initconst, so please drop this keyword.
>
OK.

> > +       MOD_CLK_BASE + R9A07G044_CRU_SYSCLK,
> > +       MOD_CLK_BASE + R9A07G044_CRU_VCLK,
> > +};
>
> I believe I haven't seen patches yet to add support for these clocks?
> Perhaps these can be combined?
>
Ahh my bad, yes the patches have not been sent out for it, I'll
combine this while adding the clocks.

Cheers,
Prabhakar
diff mbox series

Patch

diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index f5550fccb029..f923b7b3cfca 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -412,6 +412,11 @@  static const unsigned int r9a07g044_crit_mod_clks[] __initconst = {
 	MOD_CLK_BASE + R9A07G044_DMAC_ACLK,
 };
 
+static const unsigned int r9a07g044_no_pm_mod_clks[] __initconst = {
+	MOD_CLK_BASE + R9A07G044_CRU_SYSCLK,
+	MOD_CLK_BASE + R9A07G044_CRU_VCLK,
+};
+
 #ifdef CONFIG_CLK_R9A07G044
 const struct rzg2l_cpg_info r9a07g044_cpg_info = {
 	/* Core Clocks */
@@ -429,6 +434,10 @@  const struct rzg2l_cpg_info r9a07g044_cpg_info = {
 	.num_mod_clks = ARRAY_SIZE(mod_clks.common),
 	.num_hw_mod_clks = R9A07G044_TSU_PCLK + 1,
 
+	/* No PM Module Clocks */
+	.no_pm_mod_clks = r9a07g044_no_pm_mod_clks,
+	.num_no_pm_mod_clks = ARRAY_SIZE(r9a07g044_no_pm_mod_clks),
+
 	/* Resets */
 	.resets = r9a07g044_resets,
 	.num_resets = R9A07G044_TSU_PRESETN + 1, /* Last reset ID + 1 */
@@ -454,6 +463,10 @@  const struct rzg2l_cpg_info r9a07g054_cpg_info = {
 	.num_mod_clks = ARRAY_SIZE(mod_clks.common) + ARRAY_SIZE(mod_clks.drp),
 	.num_hw_mod_clks = R9A07G054_STPAI_ACLK_DRP + 1,
 
+	/* No PM Module Clocks */
+	.no_pm_mod_clks = r9a07g044_no_pm_mod_clks,
+	.num_no_pm_mod_clks = ARRAY_SIZE(r9a07g044_no_pm_mod_clks),
+
 	/* Resets */
 	.resets = r9a07g044_resets,
 	.num_resets = R9A07G054_STPAI_ARESETN + 1, /* Last reset ID + 1 */