| Message ID | 20221027123432.1818530-1-robert.foss@linaro.org (mailing list archive) |
|---|---|
| State | Awaiting Upstream, archived |
| Headers | show |
| Series | [v1,1/5] clk: qcom: dispcc-sm8250: Disable EDP_GTC for sm8350 | expand |
On 27/10/2022 15:34, Robert Foss wrote: > SM8350 does not have the EDP_GTC clock, so let's disable it > for this SoC. > > Signed-off-by: Robert Foss <robert.foss@linaro.org> > --- > drivers/clk/qcom/dispcc-sm8250.c | 3 +++ > 1 file changed, 3 insertions(+) Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c index 709076f0f9d7..180ac2726f7e 100644 --- a/drivers/clk/qcom/dispcc-sm8250.c +++ b/drivers/clk/qcom/dispcc-sm8250.c @@ -1330,6 +1330,9 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev) disp_cc_pll1_config.test_ctl_hi1_val = 0x01800000; disp_cc_pll1_init.ops = &clk_alpha_pll_lucid_5lpe_ops; disp_cc_pll1.vco_table = lucid_5lpe_vco; + + disp_cc_sm8250_clocks[DISP_CC_MDSS_EDP_GTC_CLK] = NULL; + disp_cc_sm8250_clocks[DISP_CC_MDSS_EDP_GTC_CLK_SRC] = NULL; } clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
SM8350 does not have the EDP_GTC clock, so let's disable it for this SoC. Signed-off-by: Robert Foss <robert.foss@linaro.org> --- drivers/clk/qcom/dispcc-sm8250.c | 3 +++ 1 file changed, 3 insertions(+)