| Message ID | 20221118131641.469238-2-biju.das.jz@bp.renesas.com (mailing list archive) |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | Add RZ/V2{M, MA} driver support | expand |
Hi Biju, Thanks for your patch! On Fri, Nov 18, 2022 at 2:16 PM Biju Das <biju.das.jz@bp.renesas.com> wrote: > The PWM IP on the RZ/V2M comes with 16 channels, but the ISP has > full control of channels 0 to 7, and channel 15, therefore Linux > is only allowed to use channels 8 to 14. > > The PWM channel 15 shares apb clock and reset with PWM{8..14}. > The reset is deasserted by the bootloader/ISP. Shouldn't you add the reset anyway, but make sure it stays deasserted by increasing its refcount, cfr. critical clocks? > Add PWM{8..14} clocks to CPG driver and mark apb clock as > critical clock, so that the apb clock will be always on. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > --- a/drivers/clk/renesas/r9a09g011-cpg.c > +++ b/drivers/clk/renesas/r9a09g011-cpg.c > @@ -136,6 +136,14 @@ static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = { > DEF_MOD("iic_pclk1", R9A09G011_IIC_PCLK1, CLK_SEL_E, 0x424, 12), > DEF_MOD("wdt0_pclk", R9A09G011_WDT0_PCLK, CLK_SEL_E, 0x428, 12), > DEF_MOD("wdt0_clk", R9A09G011_WDT0_CLK, CLK_MAIN, 0x428, 13), > + DEF_MOD("pwm8_15_pclk", R9A09G011_CPERI_GRPF_PCLK, CLK_SEL_E, 0x434, 0), "cperi_grpf"? > + DEF_MOD("pwm8_clk", R9A09G011_PWM8_CLK, CLK_MAIN, 0x434, 4), > + DEF_MOD("pwm9_clk", R9A09G011_PWM9_CLK, CLK_MAIN, 0x434, 5), > + DEF_MOD("pwm10_clk", R9A09G011_PWM10_CLK, CLK_MAIN, 0x434, 6), > + DEF_MOD("pwm11_clk", R9A09G011_PWM11_CLK, CLK_MAIN, 0x434, 7), > + DEF_MOD("pwm12_clk", R9A09G011_PWM12_CLK, CLK_MAIN, 0x434, 8), > + DEF_MOD("pwm13_clk", R9A09G011_PWM13_CLK, CLK_MAIN, 0x434, 9), > + DEF_MOD("pwm14_clk", R9A09G011_PWM14_CLK, CLK_MAIN, 0x434, 10), > DEF_MOD("urt_pclk", R9A09G011_URT_PCLK, CLK_SEL_E, 0x438, 4), > DEF_MOD("urt0_clk", R9A09G011_URT0_CLK, CLK_SEL_W0, 0x438, 5), > DEF_MOD("ca53", R9A09G011_CA53_CLK, CLK_DIV_A, 0x448, 0), Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Geert, Thanks for the feedback. > Subject: Re: [PATCH 1/5] clk: renesas: r9a09g011: Add PWM clock entries > > Hi Biju, > > Thanks for your patch! > > On Fri, Nov 18, 2022 at 2:16 PM Biju Das <biju.das.jz@bp.renesas.com> > wrote: > > The PWM IP on the RZ/V2M comes with 16 channels, but the ISP has full > > control of channels 0 to 7, and channel 15, therefore Linux is only > > allowed to use channels 8 to 14. > > > > The PWM channel 15 shares apb clock and reset with PWM{8..14}. > > The reset is deasserted by the bootloader/ISP. > > Shouldn't you add the reset anyway, but make sure it stays deasserted by > increasing its refcount, cfr. critical clocks? I just confused, deasserting will give some glitch on ISP, TYPE-A: A type which does not require clock supply at the time of a reset. TYPE-B: A type which requires clock supply at the time of a reset. Figure 48.6-27 TYPE-B Reset Timing by the CPG Register And Figure 48.6-28 TYPE-B Reset Timing by the Reset Source But that diagram follows a reset followed by deassert. Yes, you are correct deassert won't create any glitches. But reset followed by deassert may create clock glitch, this will be done by either ISP or bootloader. Current assumption is handling of shared resource will be handled by bootloader or ISP. Linux Just increment the refcount. OK, I will send V2 with this change. Cheers, Biju > > > Add PWM{8..14} clocks to CPG driver and mark apb clock as critical > > clock, so that the apb clock will be always on. > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > > > --- a/drivers/clk/renesas/r9a09g011-cpg.c > > +++ b/drivers/clk/renesas/r9a09g011-cpg.c > > @@ -136,6 +136,14 @@ static const struct rzg2l_mod_clk > r9a09g011_mod_clks[] __initconst = { > > DEF_MOD("iic_pclk1", R9A09G011_IIC_PCLK1, CLK_SEL_E, > 0x424, 12), > > DEF_MOD("wdt0_pclk", R9A09G011_WDT0_PCLK, CLK_SEL_E, > 0x428, 12), > > DEF_MOD("wdt0_clk", R9A09G011_WDT0_CLK, CLK_MAIN, > 0x428, 13), > > + DEF_MOD("pwm8_15_pclk", R9A09G011_CPERI_GRPF_PCLK, CLK_SEL_E, > > + 0x434, 0), > > "cperi_grpf"? > > > + DEF_MOD("pwm8_clk", R9A09G011_PWM8_CLK, CLK_MAIN, > 0x434, 4), > > + DEF_MOD("pwm9_clk", R9A09G011_PWM9_CLK, CLK_MAIN, > 0x434, 5), > > + DEF_MOD("pwm10_clk", R9A09G011_PWM10_CLK, CLK_MAIN, > 0x434, 6), > > + DEF_MOD("pwm11_clk", R9A09G011_PWM11_CLK, CLK_MAIN, > 0x434, 7), > > + DEF_MOD("pwm12_clk", R9A09G011_PWM12_CLK, CLK_MAIN, > 0x434, 8), > > + DEF_MOD("pwm13_clk", R9A09G011_PWM13_CLK, CLK_MAIN, > 0x434, 9), > > + DEF_MOD("pwm14_clk", R9A09G011_PWM14_CLK, CLK_MAIN, > 0x434, 10), > > DEF_MOD("urt_pclk", R9A09G011_URT_PCLK, CLK_SEL_E, > 0x438, 4), > > DEF_MOD("urt0_clk", R9A09G011_URT0_CLK, CLK_SEL_W0, > 0x438, 5), > > DEF_MOD("ca53", R9A09G011_CA53_CLK, CLK_DIV_A, > 0x448, 0), > > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux- > m68k.org > > In personal conversations with technical people, I call myself a hacker. > But when I'm talking to journalists I just say "programmer" or something > like that. > -- Linus Torvalds
diff --git a/drivers/clk/renesas/r9a09g011-cpg.c b/drivers/clk/renesas/r9a09g011-cpg.c index fbef1b35d254..536725762c61 100644 --- a/drivers/clk/renesas/r9a09g011-cpg.c +++ b/drivers/clk/renesas/r9a09g011-cpg.c @@ -136,6 +136,14 @@ static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = { DEF_MOD("iic_pclk1", R9A09G011_IIC_PCLK1, CLK_SEL_E, 0x424, 12), DEF_MOD("wdt0_pclk", R9A09G011_WDT0_PCLK, CLK_SEL_E, 0x428, 12), DEF_MOD("wdt0_clk", R9A09G011_WDT0_CLK, CLK_MAIN, 0x428, 13), + DEF_MOD("pwm8_15_pclk", R9A09G011_CPERI_GRPF_PCLK, CLK_SEL_E, 0x434, 0), + DEF_MOD("pwm8_clk", R9A09G011_PWM8_CLK, CLK_MAIN, 0x434, 4), + DEF_MOD("pwm9_clk", R9A09G011_PWM9_CLK, CLK_MAIN, 0x434, 5), + DEF_MOD("pwm10_clk", R9A09G011_PWM10_CLK, CLK_MAIN, 0x434, 6), + DEF_MOD("pwm11_clk", R9A09G011_PWM11_CLK, CLK_MAIN, 0x434, 7), + DEF_MOD("pwm12_clk", R9A09G011_PWM12_CLK, CLK_MAIN, 0x434, 8), + DEF_MOD("pwm13_clk", R9A09G011_PWM13_CLK, CLK_MAIN, 0x434, 9), + DEF_MOD("pwm14_clk", R9A09G011_PWM14_CLK, CLK_MAIN, 0x434, 10), DEF_MOD("urt_pclk", R9A09G011_URT_PCLK, CLK_SEL_E, 0x438, 4), DEF_MOD("urt0_clk", R9A09G011_URT0_CLK, CLK_SEL_W0, 0x438, 5), DEF_MOD("ca53", R9A09G011_CA53_CLK, CLK_DIV_A, 0x448, 0), @@ -152,6 +160,7 @@ static const struct rzg2l_reset r9a09g011_resets[] = { static const unsigned int r9a09g011_crit_mod_clks[] __initconst = { MOD_CLK_BASE + R9A09G011_CA53_CLK, + MOD_CLK_BASE + R9A09G011_CPERI_GRPF_PCLK, MOD_CLK_BASE + R9A09G011_GIC_CLK, MOD_CLK_BASE + R9A09G011_SYC_CNT_CLK, MOD_CLK_BASE + R9A09G011_URT_PCLK,
The PWM IP on the RZ/V2M comes with 16 channels, but the ISP has full control of channels 0 to 7, and channel 15, therefore Linux is only allowed to use channels 8 to 14. The PWM channel 15 shares apb clock and reset with PWM{8..14}. The reset is deasserted by the bootloader/ISP. Add PWM{8..14} clocks to CPG driver and mark apb clock as critical clock, so that the apb clock will be always on. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- drivers/clk/renesas/r9a09g011-cpg.c | 9 +++++++++ 1 file changed, 9 insertions(+)