diff mbox series

[v2,1/5] clk: renesas: r9a09g011: Add PWM clock and reset entries

Message ID 20221124191643.3193423-2-biju.das.jz@bp.renesas.com (mailing list archive)
State Awaiting Upstream, archived
Headers show
Series Add RZ/V2{M, MA} PWM driver support | expand

Commit Message

Biju Das Nov. 24, 2022, 7:16 p.m. UTC
Add PWM{8..14} clock and reset entries to CPG driver.

The PWM IP on the RZ/V2M comes with 16 channels, but the ISP has
full control of channels 0 to 7, and channel 15, therefore Linux
is only allowed to use channels 8 to 14.

The PWM channel 15 shares apb clock and reset with PWM{8..14}.
The reset is deasserted by the bootloader/ISP.

Add PWM{8..14} clocks to CPG driver and mark apb clock as
critical clock, so that the apb clock will be always on.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v1->v2:
 * Updated commit description
 * Replaced pwm8_15_pclk->cperi_grpf
 * Added reset entry R9A09G011_PWM_GPF_PRESETN
---
 drivers/clk/renesas/r9a09g011-cpg.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

Comments

Geert Uytterhoeven Dec. 1, 2022, 8:34 a.m. UTC | #1
On Thu, Nov 24, 2022 at 8:16 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Add PWM{8..14} clock and reset entries to CPG driver.
>
> The PWM IP on the RZ/V2M comes with 16 channels, but the ISP has
> full control of channels 0 to 7, and channel 15, therefore Linux
> is only allowed to use channels 8 to 14.
>
> The PWM channel 15 shares apb clock and reset with PWM{8..14}.
> The reset is deasserted by the bootloader/ISP.
>
> Add PWM{8..14} clocks to CPG driver and mark apb clock as
> critical clock, so that the apb clock will be always on.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v1->v2:
>  * Updated commit description
>  * Replaced pwm8_15_pclk->cperi_grpf
>  * Added reset entry R9A09G011_PWM_GPF_PRESETN

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk-for-v6.3.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
Geert Uytterhoeven Dec. 21, 2022, 2:10 p.m. UTC | #2
On Thu, Dec 1, 2022 at 9:34 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> On Thu, Nov 24, 2022 at 8:16 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > Add PWM{8..14} clock and reset entries to CPG driver.
> >
> > The PWM IP on the RZ/V2M comes with 16 channels, but the ISP has
> > full control of channels 0 to 7, and channel 15, therefore Linux
> > is only allowed to use channels 8 to 14.
> >
> > The PWM channel 15 shares apb clock and reset with PWM{8..14}.
> > The reset is deasserted by the bootloader/ISP.
> >
> > Add PWM{8..14} clocks to CPG driver and mark apb clock as
> > critical clock, so that the apb clock will be always on.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> > v1->v2:
> >  * Updated commit description
> >  * Replaced pwm8_15_pclk->cperi_grpf
> >  * Added reset entry R9A09G011_PWM_GPF_PRESETN
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> i.e. will queue in renesas-clk-for-v6.3.

> > @@ -147,11 +155,13 @@ static const struct rzg2l_reset r9a09g011_resets[] = {
> >         DEF_RST_MON(R9A09G011_SYC_RST_N,        0x610, 9,  13),
> >         DEF_RST(R9A09G011_IIC_GPA_PRESETN,      0x614, 8),
> >         DEF_RST(R9A09G011_IIC_GPB_PRESETN,      0x614, 9),
> > +       DEF_RST_MON(R9A09G011_PWM_GPF_PRESETN,  0x614, 5, 23),

I will move this entry up, to preserve sort order (by bit number).

> >         DEF_RST_MON(R9A09G011_WDT0_PRESETN,     0x614, 12, 19),
> >  };

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
diff mbox series

Patch

diff --git a/drivers/clk/renesas/r9a09g011-cpg.c b/drivers/clk/renesas/r9a09g011-cpg.c
index fbef1b35d254..dd5e442ec4a9 100644
--- a/drivers/clk/renesas/r9a09g011-cpg.c
+++ b/drivers/clk/renesas/r9a09g011-cpg.c
@@ -136,6 +136,14 @@  static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = {
 	DEF_MOD("iic_pclk1",	R9A09G011_IIC_PCLK1,	 CLK_SEL_E,    0x424, 12),
 	DEF_MOD("wdt0_pclk",	R9A09G011_WDT0_PCLK,	 CLK_SEL_E,    0x428, 12),
 	DEF_MOD("wdt0_clk",	R9A09G011_WDT0_CLK,	 CLK_MAIN,     0x428, 13),
+	DEF_MOD("cperi_grpf",	R9A09G011_CPERI_GRPF_PCLK, CLK_SEL_E,  0x434, 0),
+	DEF_MOD("pwm8_clk",	R9A09G011_PWM8_CLK,	 CLK_MAIN,     0x434, 4),
+	DEF_MOD("pwm9_clk",	R9A09G011_PWM9_CLK,	 CLK_MAIN,     0x434, 5),
+	DEF_MOD("pwm10_clk",	R9A09G011_PWM10_CLK,	 CLK_MAIN,     0x434, 6),
+	DEF_MOD("pwm11_clk",	R9A09G011_PWM11_CLK,	 CLK_MAIN,     0x434, 7),
+	DEF_MOD("pwm12_clk",	R9A09G011_PWM12_CLK,	 CLK_MAIN,     0x434, 8),
+	DEF_MOD("pwm13_clk",	R9A09G011_PWM13_CLK,	 CLK_MAIN,     0x434, 9),
+	DEF_MOD("pwm14_clk",	R9A09G011_PWM14_CLK,	 CLK_MAIN,     0x434, 10),
 	DEF_MOD("urt_pclk",	R9A09G011_URT_PCLK,	 CLK_SEL_E,    0x438, 4),
 	DEF_MOD("urt0_clk",	R9A09G011_URT0_CLK,	 CLK_SEL_W0,   0x438, 5),
 	DEF_MOD("ca53",		R9A09G011_CA53_CLK,	 CLK_DIV_A,    0x448, 0),
@@ -147,11 +155,13 @@  static const struct rzg2l_reset r9a09g011_resets[] = {
 	DEF_RST_MON(R9A09G011_SYC_RST_N,	0x610, 9,  13),
 	DEF_RST(R9A09G011_IIC_GPA_PRESETN,	0x614, 8),
 	DEF_RST(R9A09G011_IIC_GPB_PRESETN,	0x614, 9),
+	DEF_RST_MON(R9A09G011_PWM_GPF_PRESETN,	0x614, 5, 23),
 	DEF_RST_MON(R9A09G011_WDT0_PRESETN,	0x614, 12, 19),
 };
 
 static const unsigned int r9a09g011_crit_mod_clks[] __initconst = {
 	MOD_CLK_BASE + R9A09G011_CA53_CLK,
+	MOD_CLK_BASE + R9A09G011_CPERI_GRPF_PCLK,
 	MOD_CLK_BASE + R9A09G011_GIC_CLK,
 	MOD_CLK_BASE + R9A09G011_SYC_CNT_CLK,
 	MOD_CLK_BASE + R9A09G011_URT_PCLK,