@@ -54,6 +54,7 @@ clk50m_phy: phy-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
+ clock-output-names = "enet_ref_pad";
};
rotary-encoder {
@@ -134,6 +135,13 @@ vdiv_hitch_pos: voltage-divider-hitch-pos {
};
};
+&clks {
+ clocks = <&clk50m_phy>;
+ clock-names = "enet_ref_pad";
+ assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>;
+ assigned-clock-parents = <&clk50m_phy>;
+};
+
&ecspi2 {
cs-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
@@ -182,10 +190,6 @@ &fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rmii";
- clocks = <&clks IMX6QDL_CLK_ENET>,
- <&clks IMX6QDL_CLK_ENET>,
- <&clk50m_phy>;
- clock-names = "ipg", "ahb", "ptp";
phy-handle = <&rmii_phy>;
status = "okay";
Configure Ethernet reference clock parent in an obvious way instead of using cryptic ptp way. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> --- arch/arm/boot/dts/imx6dl-victgo.dts | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-)