From patchwork Thu Jan 26 14:40:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13117253 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1BB22C61DA2 for ; Thu, 26 Jan 2023 14:41:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232303AbjAZOlI (ORCPT ); Thu, 26 Jan 2023 09:41:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49206 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232305AbjAZOlD (ORCPT ); Thu, 26 Jan 2023 09:41:03 -0500 Received: from mail-ej1-x62f.google.com (mail-ej1-x62f.google.com [IPv6:2a00:1450:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0D8AC6AF5C for ; Thu, 26 Jan 2023 06:40:57 -0800 (PST) Received: by mail-ej1-x62f.google.com with SMTP id me3so5584875ejb.7 for ; Thu, 26 Jan 2023 06:40:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CBqQ34M24ukRM2EHUO60odWC2Bkw9VlgnSBaMsLH6+8=; b=WIHThYzfU8KFkKP7d0toaE1lOqCxHXu+M5jcMyXSf70xfOr3k/J/WCSuU8ObMXjDyc LKkvKxeCIOLVqG+XWwsC/fNWxn/nl+2yoKbitbOC+DyZgfidyNra4dmojfycTKup+fFX AL50iQzcq1x7zI2W5uHm8O1Wqf/I8Ci8tApAm0zPTDIS79fQi7adlZ0gWOK0XiDz/SlR RcbM2N1DNDG/14y9GLVL9V+cGLzGU6ZL8IglK7qUPMNbUa2kwMvVlpoUTx6zQKhTUbfH M2QV5++wqw/Z9aUcYy4Awu72Ck4JMOL3UPO7WyiY6Fgpci/7Sf13WWGdqQOZmz7ECFaY AK+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CBqQ34M24ukRM2EHUO60odWC2Bkw9VlgnSBaMsLH6+8=; b=RD9cJZ+CyEZUAtzLqKrInHnmzTr22nh3VxGY5+p/l6z7MnkjbiCi1GNHlampnOFAru mnMPVrGZROo7nsDourKCB/gvb4ldlp6J+I3dEgPl1VK8U/9z1iOkBZF4mrjTz/DnBf3f hkM8TdHjTcXKSig2vMsq7GGFi9sAL/J4kwSGUVcuVAJ+Wu0Izir+HKbFOt2yjXYTfloN UEOfr1oqHhc9WlxQ7gTaEgSMpRjwvgJaBCiq0KHX+gZoZc7LiaIbZwRuMeT++ez2ze0W KmZb2KsNVp/rSPyN9E0IApED/okdLYwmo6EGfXPwUXGZ9TzooLpVhTpCLnYifj6Y9utx pafA== X-Gm-Message-State: AO0yUKWKXM6UJUq1Zzu8mNWG4zKwThvOYxVNKzdh1fwYKimoDR1Oql57 YDOC8GPBBXwYLyILdPr53QtGPA== X-Google-Smtp-Source: AK7set/LCoQ16wv4dnkR7W+zpDqqw5Pqhcf4y7cKzur4Ajx5J8/bLCmVrvktrQJDWxh9Ydm3uAYkSg== X-Received: by 2002:a17:906:840f:b0:878:6675:d07c with SMTP id n15-20020a170906840f00b008786675d07cmr2034422ejx.37.1674744057564; Thu, 26 Jan 2023 06:40:57 -0800 (PST) Received: from localhost.localdomain (abyk108.neoplus.adsl.tpnet.pl. [83.9.30.108]) by smtp.gmail.com with ESMTPSA id s19-20020a1709060c1300b008699bacc03csm697547ejf.14.2023.01.26.06.40.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Jan 2023 06:40:57 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: marijn.suijten@somainline.org, Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/6] dt-bindings: clock: Add Qcom SM6115 GPUCC Date: Thu, 26 Jan 2023 15:40:32 +0100 Message-Id: <20230126144033.216206-6-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230126144033.216206-1-konrad.dybcio@linaro.org> References: <20230126144033.216206-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's SM6115 SoCs. Signed-off-by: Konrad Dybcio --- .../bindings/clock/qcom,sm6115-gpucc.yaml | 71 +++++++++++++++++++ include/dt-bindings/clock/qcom,sm6115-gpucc.h | 36 ++++++++++ 2 files changed, 107 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm6115-gpucc.yaml create mode 100644 include/dt-bindings/clock/qcom,sm6115-gpucc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6115-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm6115-gpucc.yaml new file mode 100644 index 000000000000..abf4e87359a3 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm6115-gpucc.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm6115-gpucc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller on SM6115 + +maintainers: + - Konrad Dybcio + +description: | + Qualcomm graphics clock control module provides clocks and power domains on + Qualcomm SoCs. + + See also:: include/dt-bindings/clock/qcom,sm6115-gpucc.h + +properties: + compatible: + enum: + - qcom,sm6115-gpucc + + clocks: + items: + - description: Board XO source + - description: GPLL0 main branch source + - description: GPLL0 main div source + + '#clock-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + '#reset-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells = <1>; + #size-cells = <1>; + + clock-controller@5990000 { + compatible = "qcom,sm6115-gpucc"; + reg = <0x05990000 0x9000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + }; +... diff --git a/include/dt-bindings/clock/qcom,sm6115-gpucc.h b/include/dt-bindings/clock/qcom,sm6115-gpucc.h new file mode 100644 index 000000000000..945f21a7d745 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm6115-gpucc.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6115_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6115_H + +/* GPU_CC clocks */ +#define GPU_CC_PLL0 0 +#define GPU_CC_PLL0_OUT_AUX2 1 +#define GPU_CC_PLL1 2 +#define GPU_CC_PLL1_OUT_AUX 3 +#define GPU_CC_AHB_CLK 4 +#define GPU_CC_CRC_AHB_CLK 5 +#define GPU_CC_CX_GFX3D_CLK 6 +#define GPU_CC_CX_GMU_CLK 7 +#define GPU_CC_CX_SNOC_DVM_CLK 8 +#define GPU_CC_CXO_AON_CLK 9 +#define GPU_CC_CXO_CLK 10 +#define GPU_CC_GMU_CLK_SRC 11 +#define GPU_CC_GX_CXO_CLK 12 +#define GPU_CC_GX_GFX3D_CLK 13 +#define GPU_CC_GX_GFX3D_CLK_SRC 14 +#define GPU_CC_SLEEP_CLK 15 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 16 + +/* Resets */ +#define GPU_GX_BCR 0 + +/* GDSCs */ +#define GPU_CX_GDSC 0 +#define GPU_GX_GDSC 1 + +#endif