| Message ID | 20230202145208.2328032-4-quic_kathirav@quicinc.com (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Headers | show |
| Series | Add APSS clock driver support for IPQ5332 | expand |
On 2.02.2023 15:52, Kathiravan T wrote: > IPQ5332 APSS PLL is of type Stromer Plus. Add support for the same. > > To configure the stromer plus PLL separate API > (clock_stromer_pll_configure) to be used. To achieve this, introduce the > new member pll_type in device data structure and call the appropriate > function based on this. > > Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com> > --- > drivers/clk/qcom/apss-ipq-pll.c | 58 ++++++++++++++++++++++++++++++++- > 1 file changed, 57 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/qcom/apss-ipq-pll.c b/drivers/clk/qcom/apss-ipq-pll.c > index 6e815e8b7fe4..023a854f2c21 100644 > --- a/drivers/clk/qcom/apss-ipq-pll.c > +++ b/drivers/clk/qcom/apss-ipq-pll.c > @@ -19,6 +19,17 @@ static const u8 ipq_pll_offsets[][PLL_OFF_MAX_REGS] = { > [PLL_OFF_TEST_CTL] = 0x30, > [PLL_OFF_TEST_CTL_U] = 0x34, > }, > + [CLK_ALPHA_PLL_TYPE_STROMER_PLUS] = { > + [PLL_OFF_L_VAL] = 0x08, > + [PLL_OFF_ALPHA_VAL] = 0x10, > + [PLL_OFF_ALPHA_VAL_U] = 0x14, > + [PLL_OFF_USER_CTL] = 0x18, > + [PLL_OFF_USER_CTL_U] = 0x1c, > + [PLL_OFF_CONFIG_CTL] = 0x20, > + [PLL_OFF_STATUS] = 0x28, > + [PLL_OFF_TEST_CTL] = 0x30, > + [PLL_OFF_TEST_CTL_U] = 0x34, > + }, Any reason this couldn't use clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS] exported from clk-alpha-pll.c? Konrad > }; > > static struct clk_alpha_pll ipq_pll_huayra = { > @@ -39,6 +50,38 @@ static struct clk_alpha_pll ipq_pll_huayra = { > }, > }; > > +static struct clk_alpha_pll ipq_pll_stromer_plus = { > + .offset = 0x0, > + .regs = ipq_pll_offsets[CLK_ALPHA_PLL_TYPE_STROMER_PLUS], > + .flags = SUPPORTS_DYNAMIC_UPDATE, > + .clkr = { > + .enable_reg = 0x0, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "a53pll", > + .parent_data = &(const struct clk_parent_data) { > + .fw_name = "xo", > + }, > + .num_parents = 1, > + .ops = &clk_alpha_pll_stromer_ops, > + }, > + }, > +}; > + > +static const struct alpha_pll_config ipq5332_pll_config = { > + .l = 0x3e, > + .config_ctl_val = 0x4001075b, > + .config_ctl_hi_val = 0x304, > + .main_output_mask = BIT(0), > + .aux_output_mask = BIT(1), > + .early_output_mask = BIT(3), > + .alpha_en_mask = BIT(24), > + .status_val = 0x3, > + .status_mask = GENMASK(10, 8), > + .lock_det = BIT(2), > + .test_ctl_hi_val = 0x00400003, > +}; > + > static const struct alpha_pll_config ipq6018_pll_config = { > .l = 0x37, > .config_ctl_val = 0x240d4828, > @@ -64,16 +107,25 @@ static const struct alpha_pll_config ipq8074_pll_config = { > }; > > struct apss_pll_data { > + int pll_type; > struct clk_alpha_pll *pll; > const struct alpha_pll_config *pll_config; > }; > > +static struct apss_pll_data ipq5332_pll_data = { > + .pll_type = CLK_ALPHA_PLL_TYPE_STROMER_PLUS, > + .pll = &ipq_pll_stromer_plus, > + .pll_config = &ipq5332_pll_config, > +}; > + > static struct apss_pll_data ipq8074_pll_data = { > + .pll_type = CLK_ALPHA_PLL_TYPE_HUAYRA, > .pll = &ipq_pll_huayra, > .pll_config = &ipq8074_pll_config, > }; > > static struct apss_pll_data ipq6018_pll_data = { > + .pll_type = CLK_ALPHA_PLL_TYPE_HUAYRA, > .pll = &ipq_pll_huayra, > .pll_config = &ipq6018_pll_config, > }; > @@ -106,7 +158,10 @@ static int apss_ipq_pll_probe(struct platform_device *pdev) > if (!data) > return -ENODEV; > > - clk_alpha_pll_configure(data->pll, regmap, data->pll_config); > + if (data->pll_type == CLK_ALPHA_PLL_TYPE_HUAYRA) > + clk_alpha_pll_configure(data->pll, regmap, data->pll_config); > + else if (data->pll_type == CLK_ALPHA_PLL_TYPE_STROMER_PLUS) > + clk_stromer_pll_configure(data->pll, regmap, data->pll_config); > > ret = devm_clk_register_regmap(dev, &data->pll->clkr); > if (ret) > @@ -117,6 +172,7 @@ static int apss_ipq_pll_probe(struct platform_device *pdev) > } > > static const struct of_device_id apss_ipq_pll_match_table[] = { > + { .compatible = "qcom,ipq5332-a53pll", .data = &ipq5332_pll_data }, > { .compatible = "qcom,ipq6018-a53pll", .data = &ipq6018_pll_data }, > { .compatible = "qcom,ipq8074-a53pll", .data = &ipq8074_pll_data }, > { }
On 2/2/2023 8:48 PM, Konrad Dybcio wrote: > > On 2.02.2023 15:52, Kathiravan T wrote: >> IPQ5332 APSS PLL is of type Stromer Plus. Add support for the same. >> >> To configure the stromer plus PLL separate API >> (clock_stromer_pll_configure) to be used. To achieve this, introduce the >> new member pll_type in device data structure and call the appropriate >> function based on this. >> >> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com> >> --- >> drivers/clk/qcom/apss-ipq-pll.c | 58 ++++++++++++++++++++++++++++++++- >> 1 file changed, 57 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/clk/qcom/apss-ipq-pll.c b/drivers/clk/qcom/apss-ipq-pll.c >> index 6e815e8b7fe4..023a854f2c21 100644 >> --- a/drivers/clk/qcom/apss-ipq-pll.c >> +++ b/drivers/clk/qcom/apss-ipq-pll.c >> @@ -19,6 +19,17 @@ static const u8 ipq_pll_offsets[][PLL_OFF_MAX_REGS] = { >> [PLL_OFF_TEST_CTL] = 0x30, >> [PLL_OFF_TEST_CTL_U] = 0x34, >> }, >> + [CLK_ALPHA_PLL_TYPE_STROMER_PLUS] = { >> + [PLL_OFF_L_VAL] = 0x08, >> + [PLL_OFF_ALPHA_VAL] = 0x10, >> + [PLL_OFF_ALPHA_VAL_U] = 0x14, >> + [PLL_OFF_USER_CTL] = 0x18, >> + [PLL_OFF_USER_CTL_U] = 0x1c, >> + [PLL_OFF_CONFIG_CTL] = 0x20, >> + [PLL_OFF_STATUS] = 0x28, >> + [PLL_OFF_TEST_CTL] = 0x30, >> + [PLL_OFF_TEST_CTL_U] = 0x34, >> + }, > Any reason this couldn't use clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS] > exported from clk-alpha-pll.c? Same reason as Huayra. The APSS PLL offset is different than the one exposed in clk-alpha-pll.c Thanks, Kathiravan T. > > Konrad >> }; >> >> static struct clk_alpha_pll ipq_pll_huayra = { >> @@ -39,6 +50,38 @@ static struct clk_alpha_pll ipq_pll_huayra = { >> }, >> }; >> >> +static struct clk_alpha_pll ipq_pll_stromer_plus = { >> + .offset = 0x0, >> + .regs = ipq_pll_offsets[CLK_ALPHA_PLL_TYPE_STROMER_PLUS], >> + .flags = SUPPORTS_DYNAMIC_UPDATE, >> + .clkr = { >> + .enable_reg = 0x0, >> + .enable_mask = BIT(0), >> + .hw.init = &(struct clk_init_data){ >> + .name = "a53pll", >> + .parent_data = &(const struct clk_parent_data) { >> + .fw_name = "xo", >> + }, >> + .num_parents = 1, >> + .ops = &clk_alpha_pll_stromer_ops, >> + }, >> + }, >> +}; >> + >> +static const struct alpha_pll_config ipq5332_pll_config = { >> + .l = 0x3e, >> + .config_ctl_val = 0x4001075b, >> + .config_ctl_hi_val = 0x304, >> + .main_output_mask = BIT(0), >> + .aux_output_mask = BIT(1), >> + .early_output_mask = BIT(3), >> + .alpha_en_mask = BIT(24), >> + .status_val = 0x3, >> + .status_mask = GENMASK(10, 8), >> + .lock_det = BIT(2), >> + .test_ctl_hi_val = 0x00400003, >> +}; >> + >> static const struct alpha_pll_config ipq6018_pll_config = { >> .l = 0x37, >> .config_ctl_val = 0x240d4828, >> @@ -64,16 +107,25 @@ static const struct alpha_pll_config ipq8074_pll_config = { >> }; >> >> struct apss_pll_data { >> + int pll_type; >> struct clk_alpha_pll *pll; >> const struct alpha_pll_config *pll_config; >> }; >> >> +static struct apss_pll_data ipq5332_pll_data = { >> + .pll_type = CLK_ALPHA_PLL_TYPE_STROMER_PLUS, >> + .pll = &ipq_pll_stromer_plus, >> + .pll_config = &ipq5332_pll_config, >> +}; >> + >> static struct apss_pll_data ipq8074_pll_data = { >> + .pll_type = CLK_ALPHA_PLL_TYPE_HUAYRA, >> .pll = &ipq_pll_huayra, >> .pll_config = &ipq8074_pll_config, >> }; >> >> static struct apss_pll_data ipq6018_pll_data = { >> + .pll_type = CLK_ALPHA_PLL_TYPE_HUAYRA, >> .pll = &ipq_pll_huayra, >> .pll_config = &ipq6018_pll_config, >> }; >> @@ -106,7 +158,10 @@ static int apss_ipq_pll_probe(struct platform_device *pdev) >> if (!data) >> return -ENODEV; >> >> - clk_alpha_pll_configure(data->pll, regmap, data->pll_config); >> + if (data->pll_type == CLK_ALPHA_PLL_TYPE_HUAYRA) >> + clk_alpha_pll_configure(data->pll, regmap, data->pll_config); >> + else if (data->pll_type == CLK_ALPHA_PLL_TYPE_STROMER_PLUS) >> + clk_stromer_pll_configure(data->pll, regmap, data->pll_config); >> >> ret = devm_clk_register_regmap(dev, &data->pll->clkr); >> if (ret) >> @@ -117,6 +172,7 @@ static int apss_ipq_pll_probe(struct platform_device *pdev) >> } >> >> static const struct of_device_id apss_ipq_pll_match_table[] = { >> + { .compatible = "qcom,ipq5332-a53pll", .data = &ipq5332_pll_data }, >> { .compatible = "qcom,ipq6018-a53pll", .data = &ipq6018_pll_data }, >> { .compatible = "qcom,ipq8074-a53pll", .data = &ipq8074_pll_data }, >> { }
diff --git a/drivers/clk/qcom/apss-ipq-pll.c b/drivers/clk/qcom/apss-ipq-pll.c index 6e815e8b7fe4..023a854f2c21 100644 --- a/drivers/clk/qcom/apss-ipq-pll.c +++ b/drivers/clk/qcom/apss-ipq-pll.c @@ -19,6 +19,17 @@ static const u8 ipq_pll_offsets[][PLL_OFF_MAX_REGS] = { [PLL_OFF_TEST_CTL] = 0x30, [PLL_OFF_TEST_CTL_U] = 0x34, }, + [CLK_ALPHA_PLL_TYPE_STROMER_PLUS] = { + [PLL_OFF_L_VAL] = 0x08, + [PLL_OFF_ALPHA_VAL] = 0x10, + [PLL_OFF_ALPHA_VAL_U] = 0x14, + [PLL_OFF_USER_CTL] = 0x18, + [PLL_OFF_USER_CTL_U] = 0x1c, + [PLL_OFF_CONFIG_CTL] = 0x20, + [PLL_OFF_STATUS] = 0x28, + [PLL_OFF_TEST_CTL] = 0x30, + [PLL_OFF_TEST_CTL_U] = 0x34, + }, }; static struct clk_alpha_pll ipq_pll_huayra = { @@ -39,6 +50,38 @@ static struct clk_alpha_pll ipq_pll_huayra = { }, }; +static struct clk_alpha_pll ipq_pll_stromer_plus = { + .offset = 0x0, + .regs = ipq_pll_offsets[CLK_ALPHA_PLL_TYPE_STROMER_PLUS], + .flags = SUPPORTS_DYNAMIC_UPDATE, + .clkr = { + .enable_reg = 0x0, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "a53pll", + .parent_data = &(const struct clk_parent_data) { + .fw_name = "xo", + }, + .num_parents = 1, + .ops = &clk_alpha_pll_stromer_ops, + }, + }, +}; + +static const struct alpha_pll_config ipq5332_pll_config = { + .l = 0x3e, + .config_ctl_val = 0x4001075b, + .config_ctl_hi_val = 0x304, + .main_output_mask = BIT(0), + .aux_output_mask = BIT(1), + .early_output_mask = BIT(3), + .alpha_en_mask = BIT(24), + .status_val = 0x3, + .status_mask = GENMASK(10, 8), + .lock_det = BIT(2), + .test_ctl_hi_val = 0x00400003, +}; + static const struct alpha_pll_config ipq6018_pll_config = { .l = 0x37, .config_ctl_val = 0x240d4828, @@ -64,16 +107,25 @@ static const struct alpha_pll_config ipq8074_pll_config = { }; struct apss_pll_data { + int pll_type; struct clk_alpha_pll *pll; const struct alpha_pll_config *pll_config; }; +static struct apss_pll_data ipq5332_pll_data = { + .pll_type = CLK_ALPHA_PLL_TYPE_STROMER_PLUS, + .pll = &ipq_pll_stromer_plus, + .pll_config = &ipq5332_pll_config, +}; + static struct apss_pll_data ipq8074_pll_data = { + .pll_type = CLK_ALPHA_PLL_TYPE_HUAYRA, .pll = &ipq_pll_huayra, .pll_config = &ipq8074_pll_config, }; static struct apss_pll_data ipq6018_pll_data = { + .pll_type = CLK_ALPHA_PLL_TYPE_HUAYRA, .pll = &ipq_pll_huayra, .pll_config = &ipq6018_pll_config, }; @@ -106,7 +158,10 @@ static int apss_ipq_pll_probe(struct platform_device *pdev) if (!data) return -ENODEV; - clk_alpha_pll_configure(data->pll, regmap, data->pll_config); + if (data->pll_type == CLK_ALPHA_PLL_TYPE_HUAYRA) + clk_alpha_pll_configure(data->pll, regmap, data->pll_config); + else if (data->pll_type == CLK_ALPHA_PLL_TYPE_STROMER_PLUS) + clk_stromer_pll_configure(data->pll, regmap, data->pll_config); ret = devm_clk_register_regmap(dev, &data->pll->clkr); if (ret) @@ -117,6 +172,7 @@ static int apss_ipq_pll_probe(struct platform_device *pdev) } static const struct of_device_id apss_ipq_pll_match_table[] = { + { .compatible = "qcom,ipq5332-a53pll", .data = &ipq5332_pll_data }, { .compatible = "qcom,ipq6018-a53pll", .data = &ipq6018_pll_data }, { .compatible = "qcom,ipq8074-a53pll", .data = &ipq8074_pll_data }, { }
IPQ5332 APSS PLL is of type Stromer Plus. Add support for the same. To configure the stromer plus PLL separate API (clock_stromer_pll_configure) to be used. To achieve this, introduce the new member pll_type in device data structure and call the appropriate function based on this. Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com> --- drivers/clk/qcom/apss-ipq-pll.c | 58 ++++++++++++++++++++++++++++++++- 1 file changed, 57 insertions(+), 1 deletion(-)