| Message ID | 20230211064006.14981-6-semen.protsenko@linaro.org (mailing list archive) |
|---|---|
| State | Awaiting Upstream, archived |
| Headers | show |
| Series | clk: samsung: exynos850: Add missing clocks for PM | expand |
> -----Original Message----- > From: Sam Protsenko <semen.protsenko@linaro.org> > Sent: Saturday, February 11, 2023 3:40 PM > To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>; Chanwoo Choi > <cw00.choi@samsung.com>; Sylwester Nawrocki <s.nawrocki@samsung.com>; Rob > Herring <robh+dt@kernel.org> > Cc: David Virag <virag.david003@gmail.com>; Chanho Park > <chanho61.park@samsung.com>; Alim Akhtar <alim.akhtar@samsung.com>; Sumit > Semwal <sumit.semwal@linaro.org>; Tomasz Figa <tomasz.figa@gmail.com>; > Michael Turquette <mturquette@baylibre.com>; Stephen Boyd > <sboyd@kernel.org>; linux-samsung-soc@vger.kernel.org; linux- > clk@vger.kernel.org; devicetree@vger.kernel.org; linux-arm- > kernel@lists.infradead.org; linux-kernel@vger.kernel.org > Subject: [PATCH 5/6] clk: samsung: exynos850: Add AUD and HSI main gate > clocks > > Add main gate clocks for controlling AUD and HSI CMUs: > - gout_aud_cmu_aud_pclk > - gout_hsi_cmu_hsi_pclk > > Those clocks were marked as CLK_IGNORE_UNUSED, as system hangs on boot > otherwise. > > While at it, add missing PPMU (Performance Profiling Monitor Unit) clocks > for CMU_HSI. > > Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> > --- > drivers/clk/samsung/clk-exynos850.c | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > > diff --git a/drivers/clk/samsung/clk-exynos850.c > b/drivers/clk/samsung/clk-exynos850.c > index a24eff42baae..3d776d57cc8f 100644 > --- a/drivers/clk/samsung/clk-exynos850.c > +++ b/drivers/clk/samsung/clk-exynos850.c > @@ -674,6 +674,7 @@ static const struct samsung_cmu_info apm_cmu_info > __initconst = { > #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4 0x2014 > #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5 0x2018 > #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6 0x201c > +#define CLK_CON_GAT_CLK_AUD_CMU_AUD_PCLK 0x2020 > #define CLK_CON_GAT_GOUT_AUD_ABOX_ACLK 0x2048 > #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY 0x204c > #define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB 0x2050 > @@ -729,6 +730,7 @@ static const unsigned long aud_clk_regs[] __initconst > = { > CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4, > CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5, > CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6, > + CLK_CON_GAT_CLK_AUD_CMU_AUD_PCLK, > CLK_CON_GAT_GOUT_AUD_ABOX_ACLK, > CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY, > CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB, > @@ -848,6 +850,9 @@ static const struct samsung_div_clock aud_div_clks[] > __initconst = { }; > > static const struct samsung_gate_clock aud_gate_clks[] __initconst = { > + GATE(CLK_GOUT_AUD_CMU_AUD_PCLK, "gout_aud_cmu_aud_pclk", > + "dout_aud_busd", > + CLK_CON_GAT_CLK_AUD_CMU_AUD_PCLK, 21, CLK_IGNORE_UNUSED, 0), > GATE(CLK_GOUT_AUD_CA32_CCLK, "gout_aud_ca32_cclk", > "mout_aud_cpu_hch", > CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32, 21, 0, 0), > GATE(CLK_GOUT_AUD_ASB_CCLK, "gout_aud_asb_cclk", > "dout_aud_cpu_aclk", @@ -1117,12 +1122,15 @@ static const struct > samsung_cmu_info g3d_cmu_info __initconst = { > #define PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER 0x0610 > #define PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER 0x0620 > #define CLK_CON_MUX_MUX_CLK_HSI_RTC 0x1000 > +#define CLK_CON_GAT_CLK_HSI_CMU_HSI_PCLK 0x2000 > #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV 0x2008 > #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50 0x200c > #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26 0x2010 > #define CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK 0x2018 > #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK 0x2024 > #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN 0x2028 > +#define CLK_CON_GAT_GOUT_HSI_PPMU_ACLK 0x202c > +#define CLK_CON_GAT_GOUT_HSI_PPMU_PCLK 0x2030 > #define CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK 0x2038 > #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20 0x203c > #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY 0x2040 > @@ -1132,12 +1140,15 @@ static const unsigned long hsi_clk_regs[] > __initconst = { > PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER, > PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER, > CLK_CON_MUX_MUX_CLK_HSI_RTC, > + CLK_CON_GAT_CLK_HSI_CMU_HSI_PCLK, > CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV, > CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50, > CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26, > CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK, > CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK, > CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN, > + CLK_CON_GAT_GOUT_HSI_PPMU_ACLK, > + CLK_CON_GAT_GOUT_HSI_PPMU_PCLK, > CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK, > CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20, > CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY, > @@ -1163,6 +1174,9 @@ static const struct samsung_mux_clock hsi_mux_clks[] > __initconst = { }; > > static const struct samsung_gate_clock hsi_gate_clks[] __initconst = { > + GATE(CLK_GOUT_HSI_CMU_HSI_PCLK, "gout_hsi_cmu_hsi_pclk", > + "mout_hsi_bus_user", > + CLK_CON_GAT_CLK_HSI_CMU_HSI_PCLK, 21, CLK_IGNORE_UNUSED, 0), You'll need to put /* TODO: */ tag or use CLK_IS_CRITICAL if you make sure it is the critical clock. > GATE(CLK_GOUT_USB_RTC_CLK, "gout_usb_rtc", "mout_hsi_rtc", > CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV, 21, 0, 0), > GATE(CLK_GOUT_USB_REF_CLK, "gout_usb_ref", "mout_hsi_usb20drd_user", > @@ -1177,6 +1191,10 @@ static const struct samsung_gate_clock > hsi_gate_clks[] __initconst = { > GATE(CLK_GOUT_MMC_CARD_SDCLKIN, "gout_mmc_card_sdclkin", > "mout_hsi_mmc_card_user", > CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN, 21, CLK_SET_RATE_PARENT, > 0), > + GATE(CLK_GOUT_HSI_PPMU_ACLK, "gout_hsi_ppmu_aclk", > "mout_hsi_bus_user", > + CLK_CON_GAT_GOUT_HSI_PPMU_ACLK, 21, 0, 0), > + GATE(CLK_GOUT_HSI_PPMU_PCLK, "gout_hsi_ppmu_pclk", > "mout_hsi_bus_user", > + CLK_CON_GAT_GOUT_HSI_PPMU_PCLK, 21, 0, 0), > GATE(CLK_GOUT_SYSREG_HSI_PCLK, "gout_sysreg_hsi_pclk", > "mout_hsi_bus_user", > CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK, 21, 0, 0), > -- > 2.39.1
On Tue, 14 Feb 2023 at 20:41, CHANHO PARK <chanho61.park@samsung.com> wrote: > > > -----Original Message----- > > From: Sam Protsenko <semen.protsenko@linaro.org> > > Sent: Saturday, February 11, 2023 3:40 PM > > To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>; Chanwoo Choi > > <cw00.choi@samsung.com>; Sylwester Nawrocki <s.nawrocki@samsung.com>; Rob > > Herring <robh+dt@kernel.org> > > Cc: David Virag <virag.david003@gmail.com>; Chanho Park > > <chanho61.park@samsung.com>; Alim Akhtar <alim.akhtar@samsung.com>; Sumit > > Semwal <sumit.semwal@linaro.org>; Tomasz Figa <tomasz.figa@gmail.com>; > > Michael Turquette <mturquette@baylibre.com>; Stephen Boyd > > <sboyd@kernel.org>; linux-samsung-soc@vger.kernel.org; linux- > > clk@vger.kernel.org; devicetree@vger.kernel.org; linux-arm- > > kernel@lists.infradead.org; linux-kernel@vger.kernel.org > > Subject: [PATCH 5/6] clk: samsung: exynos850: Add AUD and HSI main gate > > clocks > > > > Add main gate clocks for controlling AUD and HSI CMUs: > > - gout_aud_cmu_aud_pclk > > - gout_hsi_cmu_hsi_pclk > > > > Those clocks were marked as CLK_IGNORE_UNUSED, as system hangs on boot > > otherwise. > > > > While at it, add missing PPMU (Performance Profiling Monitor Unit) clocks > > for CMU_HSI. > > > > Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> > > --- > > drivers/clk/samsung/clk-exynos850.c | 18 ++++++++++++++++++ > > 1 file changed, 18 insertions(+) > > > > diff --git a/drivers/clk/samsung/clk-exynos850.c > > b/drivers/clk/samsung/clk-exynos850.c > > index a24eff42baae..3d776d57cc8f 100644 > > --- a/drivers/clk/samsung/clk-exynos850.c > > +++ b/drivers/clk/samsung/clk-exynos850.c > > @@ -674,6 +674,7 @@ static const struct samsung_cmu_info apm_cmu_info > > __initconst = { > > #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4 0x2014 > > #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5 0x2018 > > #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6 0x201c > > +#define CLK_CON_GAT_CLK_AUD_CMU_AUD_PCLK 0x2020 > > #define CLK_CON_GAT_GOUT_AUD_ABOX_ACLK 0x2048 > > #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY 0x204c > > #define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB 0x2050 > > @@ -729,6 +730,7 @@ static const unsigned long aud_clk_regs[] __initconst > > = { > > CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4, > > CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5, > > CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6, > > + CLK_CON_GAT_CLK_AUD_CMU_AUD_PCLK, > > CLK_CON_GAT_GOUT_AUD_ABOX_ACLK, > > CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY, > > CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB, > > @@ -848,6 +850,9 @@ static const struct samsung_div_clock aud_div_clks[] > > __initconst = { }; > > > > static const struct samsung_gate_clock aud_gate_clks[] __initconst = { > > + GATE(CLK_GOUT_AUD_CMU_AUD_PCLK, "gout_aud_cmu_aud_pclk", > > + "dout_aud_busd", > > + CLK_CON_GAT_CLK_AUD_CMU_AUD_PCLK, 21, CLK_IGNORE_UNUSED, 0), > > GATE(CLK_GOUT_AUD_CA32_CCLK, "gout_aud_ca32_cclk", > > "mout_aud_cpu_hch", > > CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32, 21, 0, 0), > > GATE(CLK_GOUT_AUD_ASB_CCLK, "gout_aud_asb_cclk", > > "dout_aud_cpu_aclk", @@ -1117,12 +1122,15 @@ static const struct > > samsung_cmu_info g3d_cmu_info __initconst = { > > #define PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER 0x0610 > > #define PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER 0x0620 > > #define CLK_CON_MUX_MUX_CLK_HSI_RTC 0x1000 > > +#define CLK_CON_GAT_CLK_HSI_CMU_HSI_PCLK 0x2000 > > #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV 0x2008 > > #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50 0x200c > > #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26 0x2010 > > #define CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK 0x2018 > > #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK 0x2024 > > #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN 0x2028 > > +#define CLK_CON_GAT_GOUT_HSI_PPMU_ACLK 0x202c > > +#define CLK_CON_GAT_GOUT_HSI_PPMU_PCLK 0x2030 > > #define CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK 0x2038 > > #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20 0x203c > > #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY 0x2040 > > @@ -1132,12 +1140,15 @@ static const unsigned long hsi_clk_regs[] > > __initconst = { > > PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER, > > PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER, > > CLK_CON_MUX_MUX_CLK_HSI_RTC, > > + CLK_CON_GAT_CLK_HSI_CMU_HSI_PCLK, > > CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV, > > CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50, > > CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26, > > CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK, > > CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK, > > CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN, > > + CLK_CON_GAT_GOUT_HSI_PPMU_ACLK, > > + CLK_CON_GAT_GOUT_HSI_PPMU_PCLK, > > CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK, > > CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20, > > CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY, > > @@ -1163,6 +1174,9 @@ static const struct samsung_mux_clock hsi_mux_clks[] > > __initconst = { }; > > > > static const struct samsung_gate_clock hsi_gate_clks[] __initconst = { > > + GATE(CLK_GOUT_HSI_CMU_HSI_PCLK, "gout_hsi_cmu_hsi_pclk", > > + "mout_hsi_bus_user", > > + CLK_CON_GAT_CLK_HSI_CMU_HSI_PCLK, 21, CLK_IGNORE_UNUSED, 0), > > You'll need to put /* TODO: */ tag or use CLK_IS_CRITICAL if you make sure it is the critical clock. > Thanks for the review! I'll add the comment for now, as it's done in other CMUs for similar clocks. As for making it critical: maybe I'll do it as a part of PM enablement, which I'm working on right now (if it's needed). But in that case I'd like to provide a separate patch for making all similar clocks (XXX_CMU_XXX) critical, so not in this patch. Will send v2 soon. > > GATE(CLK_GOUT_USB_RTC_CLK, "gout_usb_rtc", "mout_hsi_rtc", > > CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV, 21, 0, 0), > > GATE(CLK_GOUT_USB_REF_CLK, "gout_usb_ref", "mout_hsi_usb20drd_user", > > @@ -1177,6 +1191,10 @@ static const struct samsung_gate_clock > > hsi_gate_clks[] __initconst = { > > GATE(CLK_GOUT_MMC_CARD_SDCLKIN, "gout_mmc_card_sdclkin", > > "mout_hsi_mmc_card_user", > > CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN, 21, CLK_SET_RATE_PARENT, > > 0), > > + GATE(CLK_GOUT_HSI_PPMU_ACLK, "gout_hsi_ppmu_aclk", > > "mout_hsi_bus_user", > > + CLK_CON_GAT_GOUT_HSI_PPMU_ACLK, 21, 0, 0), > > + GATE(CLK_GOUT_HSI_PPMU_PCLK, "gout_hsi_ppmu_pclk", > > "mout_hsi_bus_user", > > + CLK_CON_GAT_GOUT_HSI_PPMU_PCLK, 21, 0, 0), > > GATE(CLK_GOUT_SYSREG_HSI_PCLK, "gout_sysreg_hsi_pclk", > > "mout_hsi_bus_user", > > CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK, 21, 0, 0), > > -- > > 2.39.1
diff --git a/drivers/clk/samsung/clk-exynos850.c b/drivers/clk/samsung/clk-exynos850.c index a24eff42baae..3d776d57cc8f 100644 --- a/drivers/clk/samsung/clk-exynos850.c +++ b/drivers/clk/samsung/clk-exynos850.c @@ -674,6 +674,7 @@ static const struct samsung_cmu_info apm_cmu_info __initconst = { #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4 0x2014 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5 0x2018 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6 0x201c +#define CLK_CON_GAT_CLK_AUD_CMU_AUD_PCLK 0x2020 #define CLK_CON_GAT_GOUT_AUD_ABOX_ACLK 0x2048 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY 0x204c #define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB 0x2050 @@ -729,6 +730,7 @@ static const unsigned long aud_clk_regs[] __initconst = { CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4, CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5, CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6, + CLK_CON_GAT_CLK_AUD_CMU_AUD_PCLK, CLK_CON_GAT_GOUT_AUD_ABOX_ACLK, CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY, CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB, @@ -848,6 +850,9 @@ static const struct samsung_div_clock aud_div_clks[] __initconst = { }; static const struct samsung_gate_clock aud_gate_clks[] __initconst = { + GATE(CLK_GOUT_AUD_CMU_AUD_PCLK, "gout_aud_cmu_aud_pclk", + "dout_aud_busd", + CLK_CON_GAT_CLK_AUD_CMU_AUD_PCLK, 21, CLK_IGNORE_UNUSED, 0), GATE(CLK_GOUT_AUD_CA32_CCLK, "gout_aud_ca32_cclk", "mout_aud_cpu_hch", CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32, 21, 0, 0), GATE(CLK_GOUT_AUD_ASB_CCLK, "gout_aud_asb_cclk", "dout_aud_cpu_aclk", @@ -1117,12 +1122,15 @@ static const struct samsung_cmu_info g3d_cmu_info __initconst = { #define PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER 0x0610 #define PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER 0x0620 #define CLK_CON_MUX_MUX_CLK_HSI_RTC 0x1000 +#define CLK_CON_GAT_CLK_HSI_CMU_HSI_PCLK 0x2000 #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV 0x2008 #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50 0x200c #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26 0x2010 #define CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK 0x2018 #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK 0x2024 #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN 0x2028 +#define CLK_CON_GAT_GOUT_HSI_PPMU_ACLK 0x202c +#define CLK_CON_GAT_GOUT_HSI_PPMU_PCLK 0x2030 #define CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK 0x2038 #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20 0x203c #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY 0x2040 @@ -1132,12 +1140,15 @@ static const unsigned long hsi_clk_regs[] __initconst = { PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER, PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER, CLK_CON_MUX_MUX_CLK_HSI_RTC, + CLK_CON_GAT_CLK_HSI_CMU_HSI_PCLK, CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV, CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50, CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26, CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK, CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK, CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN, + CLK_CON_GAT_GOUT_HSI_PPMU_ACLK, + CLK_CON_GAT_GOUT_HSI_PPMU_PCLK, CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK, CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20, CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY, @@ -1163,6 +1174,9 @@ static const struct samsung_mux_clock hsi_mux_clks[] __initconst = { }; static const struct samsung_gate_clock hsi_gate_clks[] __initconst = { + GATE(CLK_GOUT_HSI_CMU_HSI_PCLK, "gout_hsi_cmu_hsi_pclk", + "mout_hsi_bus_user", + CLK_CON_GAT_CLK_HSI_CMU_HSI_PCLK, 21, CLK_IGNORE_UNUSED, 0), GATE(CLK_GOUT_USB_RTC_CLK, "gout_usb_rtc", "mout_hsi_rtc", CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV, 21, 0, 0), GATE(CLK_GOUT_USB_REF_CLK, "gout_usb_ref", "mout_hsi_usb20drd_user", @@ -1177,6 +1191,10 @@ static const struct samsung_gate_clock hsi_gate_clks[] __initconst = { GATE(CLK_GOUT_MMC_CARD_SDCLKIN, "gout_mmc_card_sdclkin", "mout_hsi_mmc_card_user", CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN, 21, CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_HSI_PPMU_ACLK, "gout_hsi_ppmu_aclk", "mout_hsi_bus_user", + CLK_CON_GAT_GOUT_HSI_PPMU_ACLK, 21, 0, 0), + GATE(CLK_GOUT_HSI_PPMU_PCLK, "gout_hsi_ppmu_pclk", "mout_hsi_bus_user", + CLK_CON_GAT_GOUT_HSI_PPMU_PCLK, 21, 0, 0), GATE(CLK_GOUT_SYSREG_HSI_PCLK, "gout_sysreg_hsi_pclk", "mout_hsi_bus_user", CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK, 21, 0, 0),
Add main gate clocks for controlling AUD and HSI CMUs: - gout_aud_cmu_aud_pclk - gout_hsi_cmu_hsi_pclk Those clocks were marked as CLK_IGNORE_UNUSED, as system hangs on boot otherwise. While at it, add missing PPMU (Performance Profiling Monitor Unit) clocks for CMU_HSI. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> --- drivers/clk/samsung/clk-exynos850.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+)