| Message ID | 20230221024645.127922-17-hal.feng@starfivetech.com (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC | expand |
On 21/02/2023 03:46, Hal Feng wrote: > Add a new compatible string in cpu.yaml for SiFive S7 CPU > core which is used on SiFive U74-MC core complex etc. > > Signed-off-by: Hal Feng <hal.feng@starfivetech.com> > --- Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
On Tue, Feb 21, 2023 at 10:46:42AM +0800, Hal Feng wrote: > Add a new compatible string in cpu.yaml for SiFive S7 CPU > core which is used on SiFive U74-MC core complex etc. > > Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > --- > Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > index a2884e3113da..54bfe24a436b 100644 > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > @@ -35,6 +35,7 @@ properties: > - sifive,e7 > - sifive,e71 > - sifive,rocket0 > + - sifive,s7 > - sifive,u5 > - sifive,u54 > - sifive,u7 > -- > 2.38.1 > >
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index a2884e3113da..54bfe24a436b 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -35,6 +35,7 @@ properties: - sifive,e7 - sifive,e71 - sifive,rocket0 + - sifive,s7 - sifive,u5 - sifive,u54 - sifive,u7
Add a new compatible string in cpu.yaml for SiFive S7 CPU core which is used on SiFive U74-MC core complex etc. Signed-off-by: Hal Feng <hal.feng@starfivetech.com> --- Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + 1 file changed, 1 insertion(+)