| Message ID | 20230320221617.236323-6-ahalaney@redhat.com (mailing list archive) |
|---|---|
| State | Awaiting Upstream, archived |
| Headers | show |
| Series | Add EMAC3 support for sa8540p-ride | expand |
On 20.03.2023 23:16, Andrew Halaney wrote: > Add the EMAC GDSCs to allow the EMAC hardware to be enabled. > > Acked-by: Stephen Boyd <sboyd@kernel.org> > Signed-off-by: Andrew Halaney <ahalaney@redhat.com> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > > I'm still unsure if Bjorn wants to take this patch or net-dev, and how I am > supposed to indicate such other than commenting here (per Stephen's > comment on v1): https://lore.kernel.org/netdev/e5cb46e8874b12dbe438be12ee0cf949.sboyd@kernel.org/#t > > Changes since v1: > * Add Stephen's Acked-by > * Explicitly tested on x13s laptop with no noticeable side effect (Konrad) > > drivers/clk/qcom/gcc-sc8280xp.c | 18 ++++++++++++++++++ > include/dt-bindings/clock/qcom,gcc-sc8280xp.h | 2 ++ > 2 files changed, 20 insertions(+) > > diff --git a/drivers/clk/qcom/gcc-sc8280xp.c b/drivers/clk/qcom/gcc-sc8280xp.c > index b3198784e1c3..04a99dbaa57e 100644 > --- a/drivers/clk/qcom/gcc-sc8280xp.c > +++ b/drivers/clk/qcom/gcc-sc8280xp.c > @@ -6873,6 +6873,22 @@ static struct gdsc usb30_sec_gdsc = { > .pwrsts = PWRSTS_RET_ON, > }; > > +static struct gdsc emac_0_gdsc = { > + .gdscr = 0xaa004, > + .pd = { > + .name = "emac_0_gdsc", > + }, > + .pwrsts = PWRSTS_OFF_ON, > +}; > + > +static struct gdsc emac_1_gdsc = { > + .gdscr = 0xba004, > + .pd = { > + .name = "emac_1_gdsc", > + }, > + .pwrsts = PWRSTS_OFF_ON, > +}; > + > static struct clk_regmap *gcc_sc8280xp_clocks[] = { > [GCC_AGGRE_NOC_PCIE0_TUNNEL_AXI_CLK] = &gcc_aggre_noc_pcie0_tunnel_axi_clk.clkr, > [GCC_AGGRE_NOC_PCIE1_TUNNEL_AXI_CLK] = &gcc_aggre_noc_pcie1_tunnel_axi_clk.clkr, > @@ -7351,6 +7367,8 @@ static struct gdsc *gcc_sc8280xp_gdscs[] = { > [USB30_MP_GDSC] = &usb30_mp_gdsc, > [USB30_PRIM_GDSC] = &usb30_prim_gdsc, > [USB30_SEC_GDSC] = &usb30_sec_gdsc, > + [EMAC_0_GDSC] = &emac_0_gdsc, > + [EMAC_1_GDSC] = &emac_1_gdsc, > }; > > static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { > diff --git a/include/dt-bindings/clock/qcom,gcc-sc8280xp.h b/include/dt-bindings/clock/qcom,gcc-sc8280xp.h > index cb2fb638825c..721105ea4fad 100644 > --- a/include/dt-bindings/clock/qcom,gcc-sc8280xp.h > +++ b/include/dt-bindings/clock/qcom,gcc-sc8280xp.h > @@ -492,5 +492,7 @@ > #define USB30_MP_GDSC 9 > #define USB30_PRIM_GDSC 10 > #define USB30_SEC_GDSC 11 > +#define EMAC_0_GDSC 12 > +#define EMAC_1_GDSC 13 > > #endif
diff --git a/drivers/clk/qcom/gcc-sc8280xp.c b/drivers/clk/qcom/gcc-sc8280xp.c index b3198784e1c3..04a99dbaa57e 100644 --- a/drivers/clk/qcom/gcc-sc8280xp.c +++ b/drivers/clk/qcom/gcc-sc8280xp.c @@ -6873,6 +6873,22 @@ static struct gdsc usb30_sec_gdsc = { .pwrsts = PWRSTS_RET_ON, }; +static struct gdsc emac_0_gdsc = { + .gdscr = 0xaa004, + .pd = { + .name = "emac_0_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc emac_1_gdsc = { + .gdscr = 0xba004, + .pd = { + .name = "emac_1_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + static struct clk_regmap *gcc_sc8280xp_clocks[] = { [GCC_AGGRE_NOC_PCIE0_TUNNEL_AXI_CLK] = &gcc_aggre_noc_pcie0_tunnel_axi_clk.clkr, [GCC_AGGRE_NOC_PCIE1_TUNNEL_AXI_CLK] = &gcc_aggre_noc_pcie1_tunnel_axi_clk.clkr, @@ -7351,6 +7367,8 @@ static struct gdsc *gcc_sc8280xp_gdscs[] = { [USB30_MP_GDSC] = &usb30_mp_gdsc, [USB30_PRIM_GDSC] = &usb30_prim_gdsc, [USB30_SEC_GDSC] = &usb30_sec_gdsc, + [EMAC_0_GDSC] = &emac_0_gdsc, + [EMAC_1_GDSC] = &emac_1_gdsc, }; static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { diff --git a/include/dt-bindings/clock/qcom,gcc-sc8280xp.h b/include/dt-bindings/clock/qcom,gcc-sc8280xp.h index cb2fb638825c..721105ea4fad 100644 --- a/include/dt-bindings/clock/qcom,gcc-sc8280xp.h +++ b/include/dt-bindings/clock/qcom,gcc-sc8280xp.h @@ -492,5 +492,7 @@ #define USB30_MP_GDSC 9 #define USB30_PRIM_GDSC 10 #define USB30_SEC_GDSC 11 +#define EMAC_0_GDSC 12 +#define EMAC_1_GDSC 13 #endif