| Message ID | 20230403095300.3386988-2-peng.fan@oss.nxp.com (mailing list archive) |
|---|---|
| State | Awaiting Upstream, archived |
| Headers | show |
| Series | clk: imx: imx93: fix and update | expand |
On 23-04-03 17:52:54, Peng Fan (OSS) wrote: > From: Peng Fan <peng.fan@nxp.com> > > The Fvco should be range 2.4GHz to 5GHz, the original table voilate the > spec, so update the table to fix it. > > Fixes: c196175acdd3 ("clk: imx: clk-fracn-gppll: Add more freq config for video pll") > Fixes: 044034efbeea ("clk: imx: clk-fracn-gppll: fix mfd value") > Fixes: 1b26cb8a77a4 ("clk: imx: support fracn gppll") > Signed-off-by: Jacky Bai <ping.bai@nxp.com> > Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> > --- > drivers/clk/imx/clk-fracn-gppll.c | 16 +++++++++------- > 1 file changed, 9 insertions(+), 7 deletions(-) > > diff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-gppll.c > index a2aaa14fc1ae..ec50c41e2a4c 100644 > --- a/drivers/clk/imx/clk-fracn-gppll.c > +++ b/drivers/clk/imx/clk-fracn-gppll.c > @@ -60,18 +60,20 @@ struct clk_fracn_gppll { > }; > > /* > - * Fvco = Fref * (MFI + MFN / MFD) > - * Fout = Fvco / (rdiv * odiv) > + * Fvco = (Fref / rdiv) * (MFI + MFN / MFD) > + * Fout = Fvco / odiv > + * The (Fref / rdiv) should be in range 20MHz to 40MHz > + * The Fvco should be in range 2.5Ghz to 5Ghz > */ > static const struct imx_fracn_gppll_rate_table fracn_tbl[] = { > - PLL_FRACN_GP(650000000U, 81, 0, 1, 0, 3), > + PLL_FRACN_GP(650000000U, 162, 50, 100, 0, 6), > PLL_FRACN_GP(594000000U, 198, 0, 1, 0, 8), > - PLL_FRACN_GP(560000000U, 70, 0, 1, 0, 3), > - PLL_FRACN_GP(498000000U, 83, 0, 1, 0, 4), > + PLL_FRACN_GP(560000000U, 140, 0, 1, 0, 6), > + PLL_FRACN_GP(498000000U, 166, 0, 1, 0, 8), > PLL_FRACN_GP(484000000U, 121, 0, 1, 0, 6), > PLL_FRACN_GP(445333333U, 167, 0, 1, 0, 9), > - PLL_FRACN_GP(400000000U, 50, 0, 1, 0, 3), > - PLL_FRACN_GP(393216000U, 81, 92, 100, 0, 5) > + PLL_FRACN_GP(400000000U, 200, 0, 1, 0, 12), > + PLL_FRACN_GP(393216000U, 163, 84, 100, 0, 10) > }; > > struct imx_fracn_gppll_clk imx_fracn_gppll = { > -- > 2.37.1 >
diff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-gppll.c index a2aaa14fc1ae..ec50c41e2a4c 100644 --- a/drivers/clk/imx/clk-fracn-gppll.c +++ b/drivers/clk/imx/clk-fracn-gppll.c @@ -60,18 +60,20 @@ struct clk_fracn_gppll { }; /* - * Fvco = Fref * (MFI + MFN / MFD) - * Fout = Fvco / (rdiv * odiv) + * Fvco = (Fref / rdiv) * (MFI + MFN / MFD) + * Fout = Fvco / odiv + * The (Fref / rdiv) should be in range 20MHz to 40MHz + * The Fvco should be in range 2.5Ghz to 5Ghz */ static const struct imx_fracn_gppll_rate_table fracn_tbl[] = { - PLL_FRACN_GP(650000000U, 81, 0, 1, 0, 3), + PLL_FRACN_GP(650000000U, 162, 50, 100, 0, 6), PLL_FRACN_GP(594000000U, 198, 0, 1, 0, 8), - PLL_FRACN_GP(560000000U, 70, 0, 1, 0, 3), - PLL_FRACN_GP(498000000U, 83, 0, 1, 0, 4), + PLL_FRACN_GP(560000000U, 140, 0, 1, 0, 6), + PLL_FRACN_GP(498000000U, 166, 0, 1, 0, 8), PLL_FRACN_GP(484000000U, 121, 0, 1, 0, 6), PLL_FRACN_GP(445333333U, 167, 0, 1, 0, 9), - PLL_FRACN_GP(400000000U, 50, 0, 1, 0, 3), - PLL_FRACN_GP(393216000U, 81, 92, 100, 0, 5) + PLL_FRACN_GP(400000000U, 200, 0, 1, 0, 12), + PLL_FRACN_GP(393216000U, 163, 84, 100, 0, 10) }; struct imx_fracn_gppll_clk imx_fracn_gppll = {