diff mbox series

clk: qcom: mmcc-msm8974: remove oxili_ocmemgx_clk

Message ID 20230508153319.2371645-1-dmitry.baryshkov@linaro.org (mailing list archive)
State Awaiting Upstream, archived
Headers show
Series clk: qcom: mmcc-msm8974: remove oxili_ocmemgx_clk | expand

Commit Message

Dmitry Baryshkov May 8, 2023, 3:33 p.m. UTC
After the internal discussions, it looks like this clock is managed by
RPM itself. Linux kernel should not touch it on its own, as this causes
disagreement with RPM. Shutting down this clock causes the OCMEM<->GPU
interface to stop working, resulting in GPU hangchecks/timeouts.

Fixes: d8b212014e69 ("clk: qcom: Add support for MSM8974's multimedia clock controller (MMCC)")
Suggested-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/clk/qcom/mmcc-msm8974.c | 19 -------------------
 1 file changed, 19 deletions(-)

Comments

Konrad Dybcio May 8, 2023, 4:39 p.m. UTC | #1
On 8.05.2023 17:33, Dmitry Baryshkov wrote:
> After the internal discussions, it looks like this clock is managed by
> RPM itself. Linux kernel should not touch it on its own, as this causes
> disagreement with RPM. Shutting down this clock causes the OCMEM<->GPU
> interface to stop working, resulting in GPU hangchecks/timeouts.
> 
> Fixes: d8b212014e69 ("clk: qcom: Add support for MSM8974's multimedia clock controller (MMCC)")
Feels good to fix 9 year old code!

> Suggested-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
+CC Luca please give it a spin on your smartwatch

(fun to say isn't it)

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad
>  drivers/clk/qcom/mmcc-msm8974.c | 19 -------------------
>  1 file changed, 19 deletions(-)
> 
> diff --git a/drivers/clk/qcom/mmcc-msm8974.c b/drivers/clk/qcom/mmcc-msm8974.c
> index 277ef0065aae..82f6bad144a9 100644
> --- a/drivers/clk/qcom/mmcc-msm8974.c
> +++ b/drivers/clk/qcom/mmcc-msm8974.c
> @@ -2204,23 +2204,6 @@ static struct clk_branch ocmemcx_ocmemnoc_clk = {
>  	},
>  };
>  
> -static struct clk_branch oxili_ocmemgx_clk = {
> -	.halt_reg = 0x402c,
> -	.clkr = {
> -		.enable_reg = 0x402c,
> -		.enable_mask = BIT(0),
> -		.hw.init = &(struct clk_init_data){
> -			.name = "oxili_ocmemgx_clk",
> -			.parent_data = (const struct clk_parent_data[]){
> -				{ .fw_name = "gfx3d_clk_src", .name = "gfx3d_clk_src" },
> -			},
> -			.num_parents = 1,
> -			.flags = CLK_SET_RATE_PARENT,
> -			.ops = &clk_branch2_ops,
> -		},
> -	},
> -};
> -
>  static struct clk_branch ocmemnoc_clk = {
>  	.halt_reg = 0x50b4,
>  	.clkr = {
> @@ -2512,7 +2495,6 @@ static struct clk_regmap *mmcc_msm8226_clocks[] = {
>  	[MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr,
>  	[MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
>  	[OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr,
> -	[OXILI_OCMEMGX_CLK] = &oxili_ocmemgx_clk.clkr,
>  	[OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,
>  	[OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr,
>  	[OXILICX_AXI_CLK] = &oxilicx_axi_clk.clkr,
> @@ -2670,7 +2652,6 @@ static struct clk_regmap *mmcc_msm8974_clocks[] = {
>  	[MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
>  	[OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr,
>  	[OCMEMCX_OCMEMNOC_CLK] = &ocmemcx_ocmemnoc_clk.clkr,
> -	[OXILI_OCMEMGX_CLK] = &oxili_ocmemgx_clk.clkr,
>  	[OCMEMNOC_CLK] = &ocmemnoc_clk.clkr,
>  	[OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,
>  	[OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr,
Luca Weiss May 9, 2023, 4:42 p.m. UTC | #2
On Montag, 8. Mai 2023 18:39:24 CEST Konrad Dybcio wrote:
> On 8.05.2023 17:33, Dmitry Baryshkov wrote:
> > After the internal discussions, it looks like this clock is managed by
> > RPM itself. Linux kernel should not touch it on its own, as this causes
> > disagreement with RPM. Shutting down this clock causes the OCMEM<->GPU
> > interface to stop working, resulting in GPU hangchecks/timeouts.
> > 
> > Fixes: d8b212014e69 ("clk: qcom: Add support for MSM8974's multimedia
> > clock controller (MMCC)")
> Feels good to fix 9 year old code!
> 
> > Suggested-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > ---
> 
> +CC Luca please give it a spin on your smartwatch
> 
> (fun to say isn't it)

You didn't actually CC me here but appears to work fine on apq8026-lg-lenok 
with GPU. Ocmem inits fine and GPU runs fine also. No change in behavior 
observed.

Tested-by: Luca Weiss <luca@z3ntu.xyz>

(didn't try on msm8974 but should hopefully be fine there also)

> 
> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> 
> Konrad
> 
> >  drivers/clk/qcom/mmcc-msm8974.c | 19 -------------------
> >  1 file changed, 19 deletions(-)
> > 
> > diff --git a/drivers/clk/qcom/mmcc-msm8974.c
> > b/drivers/clk/qcom/mmcc-msm8974.c index 277ef0065aae..82f6bad144a9 100644
> > --- a/drivers/clk/qcom/mmcc-msm8974.c
> > +++ b/drivers/clk/qcom/mmcc-msm8974.c
> > @@ -2204,23 +2204,6 @@ static struct clk_branch ocmemcx_ocmemnoc_clk = {
> > 
> >  	},
> >  
> >  };
> > 
> > -static struct clk_branch oxili_ocmemgx_clk = {
> > -	.halt_reg = 0x402c,
> > -	.clkr = {
> > -		.enable_reg = 0x402c,
> > -		.enable_mask = BIT(0),
> > -		.hw.init = &(struct clk_init_data){
> > -			.name = "oxili_ocmemgx_clk",
> > -			.parent_data = (const struct clk_parent_data[]){
> > -				{ .fw_name = "gfx3d_clk_src", .name = 
"gfx3d_clk_src" },
> > -			},
> > -			.num_parents = 1,
> > -			.flags = CLK_SET_RATE_PARENT,
> > -			.ops = &clk_branch2_ops,
> > -		},
> > -	},
> > -};
> > -
> > 
> >  static struct clk_branch ocmemnoc_clk = {
> >  
> >  	.halt_reg = 0x50b4,
> >  	.clkr = {
> > 
> > @@ -2512,7 +2495,6 @@ static struct clk_regmap *mmcc_msm8226_clocks[] = {
> > 
> >  	[MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr,
> >  	[MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
> >  	[OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr,
> > 
> > -	[OXILI_OCMEMGX_CLK] = &oxili_ocmemgx_clk.clkr,
> > 
> >  	[OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,
> >  	[OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr,
> >  	[OXILICX_AXI_CLK] = &oxilicx_axi_clk.clkr,
> > 
> > @@ -2670,7 +2652,6 @@ static struct clk_regmap *mmcc_msm8974_clocks[] = {
> > 
> >  	[MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
> >  	[OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr,
> >  	[OCMEMCX_OCMEMNOC_CLK] = &ocmemcx_ocmemnoc_clk.clkr,
> > 
> > -	[OXILI_OCMEMGX_CLK] = &oxili_ocmemgx_clk.clkr,
> > 
> >  	[OCMEMNOC_CLK] = &ocmemnoc_clk.clkr,
> >  	[OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,
> >  	[OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr,
Bjorn Andersson May 25, 2023, 4:53 a.m. UTC | #3
On Mon, 8 May 2023 18:33:19 +0300, Dmitry Baryshkov wrote:
> After the internal discussions, it looks like this clock is managed by
> RPM itself. Linux kernel should not touch it on its own, as this causes
> disagreement with RPM. Shutting down this clock causes the OCMEM<->GPU
> interface to stop working, resulting in GPU hangchecks/timeouts.
> 
> 

Applied, thanks!

[1/1] clk: qcom: mmcc-msm8974: remove oxili_ocmemgx_clk
      commit: 853c064b57491d739bfd0cc35ff75c5ea9c5e8f5

Best regards,
diff mbox series

Patch

diff --git a/drivers/clk/qcom/mmcc-msm8974.c b/drivers/clk/qcom/mmcc-msm8974.c
index 277ef0065aae..82f6bad144a9 100644
--- a/drivers/clk/qcom/mmcc-msm8974.c
+++ b/drivers/clk/qcom/mmcc-msm8974.c
@@ -2204,23 +2204,6 @@  static struct clk_branch ocmemcx_ocmemnoc_clk = {
 	},
 };
 
-static struct clk_branch oxili_ocmemgx_clk = {
-	.halt_reg = 0x402c,
-	.clkr = {
-		.enable_reg = 0x402c,
-		.enable_mask = BIT(0),
-		.hw.init = &(struct clk_init_data){
-			.name = "oxili_ocmemgx_clk",
-			.parent_data = (const struct clk_parent_data[]){
-				{ .fw_name = "gfx3d_clk_src", .name = "gfx3d_clk_src" },
-			},
-			.num_parents = 1,
-			.flags = CLK_SET_RATE_PARENT,
-			.ops = &clk_branch2_ops,
-		},
-	},
-};
-
 static struct clk_branch ocmemnoc_clk = {
 	.halt_reg = 0x50b4,
 	.clkr = {
@@ -2512,7 +2495,6 @@  static struct clk_regmap *mmcc_msm8226_clocks[] = {
 	[MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr,
 	[MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
 	[OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr,
-	[OXILI_OCMEMGX_CLK] = &oxili_ocmemgx_clk.clkr,
 	[OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,
 	[OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr,
 	[OXILICX_AXI_CLK] = &oxilicx_axi_clk.clkr,
@@ -2670,7 +2652,6 @@  static struct clk_regmap *mmcc_msm8974_clocks[] = {
 	[MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
 	[OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr,
 	[OCMEMCX_OCMEMNOC_CLK] = &ocmemcx_ocmemnoc_clk.clkr,
-	[OXILI_OCMEMGX_CLK] = &oxili_ocmemgx_clk.clkr,
 	[OCMEMNOC_CLK] = &ocmemnoc_clk.clkr,
 	[OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,
 	[OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr,