| Message ID | 20230509161218.11979-3-quic_jkona@quicinc.com (mailing list archive) |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | Add Video Clock Controller driver for SM8550 | expand |
On 09/05/2023 18:12, Jagadeesh Kona wrote: > Add device tree bindings for the video clock controller on Qualcomm > SM8550 platform. > > Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> > Signed-off-by: Taniya Das <quic_tdas@quicinc.com> > --- > .../bindings/clock/qcom,sm8550-videocc.yaml | 77 +++++++++++++++++++ > .../dt-bindings/clock/qcom,sm8550-videocc.h | 38 +++++++++ > 2 files changed, 115 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm8550-videocc.yaml > create mode 100644 include/dt-bindings/clock/qcom,sm8550-videocc.h > > diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-videocc.yaml > new file mode 100644 > index 000000000000..107af5e9af89 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-videocc.yaml > @@ -0,0 +1,77 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/qcom,sm8550-videocc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm Video Clock & Reset Controller on SM8550 > + > +maintainers: > + - Jagadeesh Kona <quic_jkona@quicinc.com> > + - Taniya Das <quic_tdas@quicinc.com> > + > +description: | > + Qualcomm video clock control module provides the clocks, resets and power > + domains on SM8550. > + > + See also:: include/dt-bindings/clock/qcom,videocc-sm8550.h > + > +properties: > + compatible: > + const: qcom,sm8550-videocc Nope, looks 100% the same as sm8450, put it there. https://lore.kernel.org/all/20230509172148.7627-2-quic_tdas@quicinc.com/ Best regards, Krzysztof
Hi, Thanks Krzysztof for your review! On 5/10/2023 12:43 PM, Krzysztof Kozlowski wrote: > On 09/05/2023 18:12, Jagadeesh Kona wrote: >> Add device tree bindings for the video clock controller on Qualcomm >> SM8550 platform. >> >> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> >> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> >> --- >> .../bindings/clock/qcom,sm8550-videocc.yaml | 77 +++++++++++++++++++ >> .../dt-bindings/clock/qcom,sm8550-videocc.h | 38 +++++++++ >> 2 files changed, 115 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm8550-videocc.yaml >> create mode 100644 include/dt-bindings/clock/qcom,sm8550-videocc.h >> >> diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-videocc.yaml >> new file mode 100644 >> index 000000000000..107af5e9af89 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-videocc.yaml >> @@ -0,0 +1,77 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/clock/qcom,sm8550-videocc.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Qualcomm Video Clock & Reset Controller on SM8550 >> + >> +maintainers: >> + - Jagadeesh Kona <quic_jkona@quicinc.com> >> + - Taniya Das <quic_tdas@quicinc.com> >> + >> +description: | >> + Qualcomm video clock control module provides the clocks, resets and power >> + domains on SM8550. >> + >> + See also:: include/dt-bindings/clock/qcom,videocc-sm8550.h >> + >> +properties: >> + compatible: >> + const: qcom,sm8550-videocc > > Nope, looks 100% the same as sm8450, put it there. > > https://lore.kernel.org/all/20230509172148.7627-2-quic_tdas@quicinc.com/ > Yes, will take care of this in next series. > Best regards, > Krzysztof > Thanks & Regards, Jagadeesh
diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-videocc.yaml new file mode 100644 index 000000000000..107af5e9af89 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-videocc.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm8550-videocc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Video Clock & Reset Controller on SM8550 + +maintainers: + - Jagadeesh Kona <quic_jkona@quicinc.com> + - Taniya Das <quic_tdas@quicinc.com> + +description: | + Qualcomm video clock control module provides the clocks, resets and power + domains on SM8550. + + See also:: include/dt-bindings/clock/qcom,videocc-sm8550.h + +properties: + compatible: + const: qcom,sm8550-videocc + + reg: + maxItems: 1 + + clocks: + items: + - description: Board XO source + - description: Video AHB clock from GCC + + power-domains: + maxItems: 1 + description: + MMCX power domain. + + required-opps: + maxItems: 1 + description: + A phandle to an OPP node describing required MMCX performance point. + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - power-domains + - required-opps + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,sm8550-gcc.h> + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/power/qcom-rpmpd.h> + videocc: clock-controller@aaf0000 { + compatible = "qcom,sm8550-videocc"; + reg = <0x0aaf0000 0x10000>; + clocks = <&bi_tcxo_div2>, <&gcc GCC_VIDEO_AHB_CLK>; + power-domains = <&rpmhpd SM8550_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,sm8550-videocc.h b/include/dt-bindings/clock/qcom,sm8550-videocc.h new file mode 100644 index 000000000000..ee5efb5be9a8 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm8550-videocc.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8550_H +#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8550_H + +/* VIDEO_CC clocks */ +#define VIDEO_CC_PLL0 0 +#define VIDEO_CC_PLL1 1 +#define VIDEO_CC_MVS0_CLK 2 +#define VIDEO_CC_MVS0_CLK_SRC 3 +#define VIDEO_CC_MVS0_DIV_CLK_SRC 4 +#define VIDEO_CC_MVS0C_CLK 5 +#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 6 +#define VIDEO_CC_MVS1_CLK 7 +#define VIDEO_CC_MVS1_CLK_SRC 8 +#define VIDEO_CC_MVS1_DIV_CLK_SRC 9 +#define VIDEO_CC_MVS1C_CLK 10 +#define VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC 11 + +/* VIDEO_CC power domains */ +#define VIDEO_CC_MVS0C_GDSC 0 +#define VIDEO_CC_MVS0_GDSC 1 +#define VIDEO_CC_MVS1C_GDSC 2 +#define VIDEO_CC_MVS1_GDSC 3 + +/* VIDEO_CC resets */ +#define CVP_VIDEO_CC_INTERFACE_BCR 0 +#define CVP_VIDEO_CC_MVS0_BCR 1 +#define CVP_VIDEO_CC_MVS0C_BCR 2 +#define CVP_VIDEO_CC_MVS1_BCR 3 +#define CVP_VIDEO_CC_MVS1C_BCR 4 +#define VIDEO_CC_MVS0C_CLK_ARES 5 +#define VIDEO_CC_MVS1C_CLK_ARES 6 + +#endif