From patchwork Tue May 9 16:12:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagadeesh Kona X-Patchwork-Id: 13235935 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EB477C7EE24 for ; Tue, 9 May 2023 16:14:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235930AbjEIQOA (ORCPT ); Tue, 9 May 2023 12:14:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39950 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235905AbjEIQNy (ORCPT ); Tue, 9 May 2023 12:13:54 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 389384225; Tue, 9 May 2023 09:13:52 -0700 (PDT) Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 349DCEVo026716; Tue, 9 May 2023 16:13:47 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=tVq60fe2dc3Vb1yCJ76u7DNpIiVlS7dd8G3rUejdNes=; b=TN79ycf/3A/9R7nVhhD24B8Q4nlbjtDfIWs7Tu4SuzpcJChr6L7rwKJqOH81/w24H96N cUGHmpZ/t8kg20/hNkP1Hxp+J6S3p5i6Mk0jIpDSFcXlvQgNmcipBUaP9hjjGYzh9hI8 9BanUqBOzMcy6ZNAnN8x7uqEY1yAQ+tSwhRL6d+0/FBSW7F/XSUpYjIdkUb6PujtdP+X 00/5rUKj1tXuCHWFAdWgTyYOFIBYuagLSShDsEqYWVWLKNgJdz44355YJKfbTWakJjcK MacT+llZdlZUKRmd9W0b/T4AP0aLT/nCPBjVUeXXSU6w8c02JkQHqpH0zUjLI+MRCOwK ig== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3qf77j2acm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 09 May 2023 16:13:46 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 349GDj1Y016620 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 9 May 2023 16:13:45 GMT Received: from hu-jkona-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Tue, 9 May 2023 09:13:10 -0700 From: Jagadeesh Kona To: Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Michael Turquette , Conor Dooley CC: Bjorn Andersson , Konrad Dybcio , Jagadeesh Kona , "Taniya Das" , , , , Subject: [PATCH 2/4] dt-bindings: clock: qcom: Add SM8550 video clock controller Date: Tue, 9 May 2023 21:42:16 +0530 Message-ID: <20230509161218.11979-3-quic_jkona@quicinc.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230509161218.11979-1-quic_jkona@quicinc.com> References: <20230509161218.11979-1-quic_jkona@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: t9R3MIQ0niS_enQWI-sa9UUYeW6xbxc- X-Proofpoint-GUID: t9R3MIQ0niS_enQWI-sa9UUYeW6xbxc- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-09_09,2023-05-05_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 mlxscore=0 bulkscore=0 phishscore=0 lowpriorityscore=0 clxscore=1015 mlxlogscore=999 adultscore=0 suspectscore=0 priorityscore=1501 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305090133 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add device tree bindings for the video clock controller on Qualcomm SM8550 platform. Signed-off-by: Jagadeesh Kona Signed-off-by: Taniya Das --- .../bindings/clock/qcom,sm8550-videocc.yaml | 77 +++++++++++++++++++ .../dt-bindings/clock/qcom,sm8550-videocc.h | 38 +++++++++ 2 files changed, 115 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm8550-videocc.yaml create mode 100644 include/dt-bindings/clock/qcom,sm8550-videocc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-videocc.yaml new file mode 100644 index 000000000000..107af5e9af89 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-videocc.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm8550-videocc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Video Clock & Reset Controller on SM8550 + +maintainers: + - Jagadeesh Kona + - Taniya Das + +description: | + Qualcomm video clock control module provides the clocks, resets and power + domains on SM8550. + + See also:: include/dt-bindings/clock/qcom,videocc-sm8550.h + +properties: + compatible: + const: qcom,sm8550-videocc + + reg: + maxItems: 1 + + clocks: + items: + - description: Board XO source + - description: Video AHB clock from GCC + + power-domains: + maxItems: 1 + description: + MMCX power domain. + + required-opps: + maxItems: 1 + description: + A phandle to an OPP node describing required MMCX performance point. + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - power-domains + - required-opps + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include + #include + #include + videocc: clock-controller@aaf0000 { + compatible = "qcom,sm8550-videocc"; + reg = <0x0aaf0000 0x10000>; + clocks = <&bi_tcxo_div2>, <&gcc GCC_VIDEO_AHB_CLK>; + power-domains = <&rpmhpd SM8550_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,sm8550-videocc.h b/include/dt-bindings/clock/qcom,sm8550-videocc.h new file mode 100644 index 000000000000..ee5efb5be9a8 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm8550-videocc.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8550_H +#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8550_H + +/* VIDEO_CC clocks */ +#define VIDEO_CC_PLL0 0 +#define VIDEO_CC_PLL1 1 +#define VIDEO_CC_MVS0_CLK 2 +#define VIDEO_CC_MVS0_CLK_SRC 3 +#define VIDEO_CC_MVS0_DIV_CLK_SRC 4 +#define VIDEO_CC_MVS0C_CLK 5 +#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 6 +#define VIDEO_CC_MVS1_CLK 7 +#define VIDEO_CC_MVS1_CLK_SRC 8 +#define VIDEO_CC_MVS1_DIV_CLK_SRC 9 +#define VIDEO_CC_MVS1C_CLK 10 +#define VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC 11 + +/* VIDEO_CC power domains */ +#define VIDEO_CC_MVS0C_GDSC 0 +#define VIDEO_CC_MVS0_GDSC 1 +#define VIDEO_CC_MVS1C_GDSC 2 +#define VIDEO_CC_MVS1_GDSC 3 + +/* VIDEO_CC resets */ +#define CVP_VIDEO_CC_INTERFACE_BCR 0 +#define CVP_VIDEO_CC_MVS0_BCR 1 +#define CVP_VIDEO_CC_MVS0C_BCR 2 +#define CVP_VIDEO_CC_MVS1_BCR 3 +#define CVP_VIDEO_CC_MVS1C_BCR 4 +#define VIDEO_CC_MVS0C_CLK_ARES 5 +#define VIDEO_CC_MVS1C_CLK_ARES 6 + +#endif