| Message ID | 20230518101234.143748-10-xingyu.wu@starfivetech.com (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | Add STG/ISP/VOUT clock and reset drivers for StarFive JH7110 | expand |
On Thu, May 18, 2023 at 06:12:32PM +0800, Xingyu Wu wrote: > From: Walker Chen <walker.chen@starfivetech.com> > > Add the pmu controller node for the Starfive JH7110 SoC. The PMU needs > to be used by other modules such as VPU, ISP, etc. > > Signed-off-by: Walker Chen <walker.chen@starfivetech.com> Firstly, this is missing your SoB - but more importantly this is already in my tree as 6a887bcc4138 ("riscv: dts: starfive: Add PMU controller node"). Thanks, Conor. > --- > arch/riscv/boot/dts/starfive/jh7110.dtsi | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi > index 4c5fdb905da8..30e1f34d5cf8 100644 > --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi > @@ -496,5 +496,12 @@ aongpio: pinctrl@17020000 { > gpio-controller; > #gpio-cells = <2>; > }; > + > + pwrc: power-controller@17030000 { > + compatible = "starfive,jh7110-pmu"; > + reg = <0x0 0x17030000 0x0 0x10000>; > + interrupts = <111>; > + #power-domain-cells = <1>; > + }; > }; > }; > -- > 2.25.1 >
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 4c5fdb905da8..30e1f34d5cf8 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -496,5 +496,12 @@ aongpio: pinctrl@17020000 { gpio-controller; #gpio-cells = <2>; }; + + pwrc: power-controller@17030000 { + compatible = "starfive,jh7110-pmu"; + reg = <0x0 0x17030000 0x0 0x10000>; + interrupts = <111>; + #power-domain-cells = <1>; + }; }; };