| Message ID | 20230609115058.9059-5-quic_jkona@quicinc.com (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | Add camera clock controller support for SM8550 | expand |
On 9.06.2023 13:50, Jagadeesh Kona wrote: > Add device node for camera clock controller on Qualcomm > SM8550 platform. > > Signed-off-by: Taniya Das <quic_tdas@quicinc.com> > Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> > --- > Changes since V3: > - No changes > Changes since V2: > - No changes > Changes since V1: > - Padded non-zero address part to 8 hex digits > > arch/arm64/boot/dts/qcom/sm8550.dtsi | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi > index 75cd374943eb..4d2d610fc66a 100644 > --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi > @@ -5,6 +5,7 @@ > > #include <dt-bindings/clock/qcom,rpmh.h> > #include <dt-bindings/clock/qcom,sm8450-videocc.h> > +#include <dt-bindings/clock/qcom,sm8550-camcc.h> > #include <dt-bindings/clock/qcom,sm8550-gcc.h> > #include <dt-bindings/clock/qcom,sm8550-gpucc.h> > #include <dt-bindings/clock/qcom,sm8550-tcsr.h> > @@ -2419,6 +2420,20 @@ videocc: clock-controller@aaf0000 { > #power-domain-cells = <1>; > }; > > + camcc: clock-controller@ade0000 { > + compatible = "qcom,sm8550-camcc"; > + reg = <0 0x0ade0000 0 0x20000>; > + clocks = <&gcc GCC_CAMERA_AHB_CLK>, > + <&bi_tcxo_div2>, > + <&bi_tcxo_ao_div2>, > + <&sleep_clk>; > + power-domains = <&rpmhpd SM8550_MMCX>; I see that both MMCX ("mmcx.lvl") and MXC ("mxc.lvl") (and MX, FWIW) are consumed on msm-5.15, with the latter one powering camcc PLLs.. How are they related? Is that resolved internally or does it need manual intervention? Konrad > + required-opps = <&rpmhpd_opp_low_svs>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + #power-domain-cells = <1>; > + }; > + > mdss: display-subsystem@ae00000 { > compatible = "qcom,sm8550-mdss"; > reg = <0 0x0ae00000 0 0x1000>;
On 6/9/2023 6:22 PM, Konrad Dybcio wrote: > > > On 9.06.2023 13:50, Jagadeesh Kona wrote: >> Add device node for camera clock controller on Qualcomm >> SM8550 platform. >> >> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> >> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> >> --- >> Changes since V3: >> - No changes >> Changes since V2: >> - No changes >> Changes since V1: >> - Padded non-zero address part to 8 hex digits >> >> arch/arm64/boot/dts/qcom/sm8550.dtsi | 15 +++++++++++++++ >> 1 file changed, 15 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi >> index 75cd374943eb..4d2d610fc66a 100644 >> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi >> @@ -5,6 +5,7 @@ >> >> #include <dt-bindings/clock/qcom,rpmh.h> >> #include <dt-bindings/clock/qcom,sm8450-videocc.h> >> +#include <dt-bindings/clock/qcom,sm8550-camcc.h> >> #include <dt-bindings/clock/qcom,sm8550-gcc.h> >> #include <dt-bindings/clock/qcom,sm8550-gpucc.h> >> #include <dt-bindings/clock/qcom,sm8550-tcsr.h> >> @@ -2419,6 +2420,20 @@ videocc: clock-controller@aaf0000 { >> #power-domain-cells = <1>; >> }; >> >> + camcc: clock-controller@ade0000 { >> + compatible = "qcom,sm8550-camcc"; >> + reg = <0 0x0ade0000 0 0x20000>; >> + clocks = <&gcc GCC_CAMERA_AHB_CLK>, >> + <&bi_tcxo_div2>, >> + <&bi_tcxo_ao_div2>, >> + <&sleep_clk>; >> + power-domains = <&rpmhpd SM8550_MMCX>; > I see that both MMCX ("mmcx.lvl") and MXC ("mxc.lvl") (and MX, FWIW) > are consumed on msm-5.15, with the latter one powering camcc PLLs.. > > How are they related? Is that resolved internally or does it need > manual intervention? > > Konrad These are just different voltage rails, camcc clocks are powered by MMCX rail and camcc pll's are powered by MXC rail. Consumer drivers need to take care of voting on these rails properly based on the frequency of clocks requested. Thanks, Jagadeesh >> + required-opps = <&rpmhpd_opp_low_svs>; >> + #clock-cells = <1>; >> + #reset-cells = <1>; >> + #power-domain-cells = <1>; >> + }; >> + >> mdss: display-subsystem@ae00000 { >> compatible = "qcom,sm8550-mdss"; >> reg = <0 0x0ae00000 0 0x1000>;
On Wed, 14 Jun 2023 at 14:56, Jagadeesh Kona <quic_jkona@quicinc.com> wrote: > > > > On 6/9/2023 6:22 PM, Konrad Dybcio wrote: > > > > > > On 9.06.2023 13:50, Jagadeesh Kona wrote: > >> Add device node for camera clock controller on Qualcomm > >> SM8550 platform. > >> > >> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> > >> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> > >> --- > >> Changes since V3: > >> - No changes > >> Changes since V2: > >> - No changes > >> Changes since V1: > >> - Padded non-zero address part to 8 hex digits > >> > >> arch/arm64/boot/dts/qcom/sm8550.dtsi | 15 +++++++++++++++ > >> 1 file changed, 15 insertions(+) > >> > >> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi > >> index 75cd374943eb..4d2d610fc66a 100644 > >> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi > >> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi > >> @@ -5,6 +5,7 @@ > >> > >> #include <dt-bindings/clock/qcom,rpmh.h> > >> #include <dt-bindings/clock/qcom,sm8450-videocc.h> > >> +#include <dt-bindings/clock/qcom,sm8550-camcc.h> > >> #include <dt-bindings/clock/qcom,sm8550-gcc.h> > >> #include <dt-bindings/clock/qcom,sm8550-gpucc.h> > >> #include <dt-bindings/clock/qcom,sm8550-tcsr.h> > >> @@ -2419,6 +2420,20 @@ videocc: clock-controller@aaf0000 { > >> #power-domain-cells = <1>; > >> }; > >> > >> + camcc: clock-controller@ade0000 { > >> + compatible = "qcom,sm8550-camcc"; > >> + reg = <0 0x0ade0000 0 0x20000>; > >> + clocks = <&gcc GCC_CAMERA_AHB_CLK>, > >> + <&bi_tcxo_div2>, > >> + <&bi_tcxo_ao_div2>, > >> + <&sleep_clk>; > >> + power-domains = <&rpmhpd SM8550_MMCX>; > > I see that both MMCX ("mmcx.lvl") and MXC ("mxc.lvl") (and MX, FWIW) > > are consumed on msm-5.15, with the latter one powering camcc PLLs.. > > > > How are they related? Is that resolved internally or does it need > > manual intervention? > > > > Konrad > > These are just different voltage rails, camcc clocks are powered by MMCX > rail and camcc pll's are powered by MXC rail. Consumer drivers need to > take care of voting on these rails properly based on the frequency of > clocks requested. Which rail powers registers of the camcc? Which rail is required to read PLL registers? > > Thanks, > Jagadeesh > > >> + required-opps = <&rpmhpd_opp_low_svs>; > >> + #clock-cells = <1>; > >> + #reset-cells = <1>; > >> + #power-domain-cells = <1>; > >> + }; > >> + > >> mdss: display-subsystem@ae00000 { > >> compatible = "qcom,sm8550-mdss"; > >> reg = <0 0x0ae00000 0 0x1000>;
On 6/14/2023 5:45 PM, Dmitry Baryshkov wrote: > On Wed, 14 Jun 2023 at 14:56, Jagadeesh Kona <quic_jkona@quicinc.com> wrote: >> >> >> >> On 6/9/2023 6:22 PM, Konrad Dybcio wrote: >>> >>> >>> On 9.06.2023 13:50, Jagadeesh Kona wrote: >>>> Add device node for camera clock controller on Qualcomm >>>> SM8550 platform. >>>> >>>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> >>>> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> >>>> --- >>>> Changes since V3: >>>> - No changes >>>> Changes since V2: >>>> - No changes >>>> Changes since V1: >>>> - Padded non-zero address part to 8 hex digits >>>> >>>> arch/arm64/boot/dts/qcom/sm8550.dtsi | 15 +++++++++++++++ >>>> 1 file changed, 15 insertions(+) >>>> >>>> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi >>>> index 75cd374943eb..4d2d610fc66a 100644 >>>> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi >>>> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi >>>> @@ -5,6 +5,7 @@ >>>> >>>> #include <dt-bindings/clock/qcom,rpmh.h> >>>> #include <dt-bindings/clock/qcom,sm8450-videocc.h> >>>> +#include <dt-bindings/clock/qcom,sm8550-camcc.h> >>>> #include <dt-bindings/clock/qcom,sm8550-gcc.h> >>>> #include <dt-bindings/clock/qcom,sm8550-gpucc.h> >>>> #include <dt-bindings/clock/qcom,sm8550-tcsr.h> >>>> @@ -2419,6 +2420,20 @@ videocc: clock-controller@aaf0000 { >>>> #power-domain-cells = <1>; >>>> }; >>>> >>>> + camcc: clock-controller@ade0000 { >>>> + compatible = "qcom,sm8550-camcc"; >>>> + reg = <0 0x0ade0000 0 0x20000>; >>>> + clocks = <&gcc GCC_CAMERA_AHB_CLK>, >>>> + <&bi_tcxo_div2>, >>>> + <&bi_tcxo_ao_div2>, >>>> + <&sleep_clk>; >>>> + power-domains = <&rpmhpd SM8550_MMCX>; >>> I see that both MMCX ("mmcx.lvl") and MXC ("mxc.lvl") (and MX, FWIW) >>> are consumed on msm-5.15, with the latter one powering camcc PLLs.. >>> >>> How are they related? Is that resolved internally or does it need >>> manual intervention? >>> >>> Konrad >> >> These are just different voltage rails, camcc clocks are powered by MMCX >> rail and camcc pll's are powered by MXC rail. Consumer drivers need to >> take care of voting on these rails properly based on the frequency of >> clocks requested. > > Which rail powers registers of the camcc? Which rail is required to > read PLL registers? > MMCX rail is required to access camcc registers, both MMCX and MXC are required to read PLL registers. MXC rail should be left ON from bootloaders during bootup and hence does not require explicit voting. Thanks, Jagadeesh >> >> Thanks, >> Jagadeesh >> >>>> + required-opps = <&rpmhpd_opp_low_svs>; >>>> + #clock-cells = <1>; >>>> + #reset-cells = <1>; >>>> + #power-domain-cells = <1>; >>>> + }; >>>> + >>>> mdss: display-subsystem@ae00000 { >>>> compatible = "qcom,sm8550-mdss"; >>>> reg = <0 0x0ae00000 0 0x1000>; > > >
On 23.06.2023 18:45, Jagadeesh Kona wrote: > > > On 6/14/2023 5:45 PM, Dmitry Baryshkov wrote: >> On Wed, 14 Jun 2023 at 14:56, Jagadeesh Kona <quic_jkona@quicinc.com> wrote: >>> >>> >>> >>> On 6/9/2023 6:22 PM, Konrad Dybcio wrote: >>>> >>>> >>>> On 9.06.2023 13:50, Jagadeesh Kona wrote: >>>>> Add device node for camera clock controller on Qualcomm >>>>> SM8550 platform. >>>>> >>>>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> >>>>> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> >>>>> --- >>>>> Changes since V3: >>>>> - No changes >>>>> Changes since V2: >>>>> - No changes >>>>> Changes since V1: >>>>> - Padded non-zero address part to 8 hex digits >>>>> >>>>> arch/arm64/boot/dts/qcom/sm8550.dtsi | 15 +++++++++++++++ >>>>> 1 file changed, 15 insertions(+) >>>>> >>>>> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi >>>>> index 75cd374943eb..4d2d610fc66a 100644 >>>>> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi >>>>> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi >>>>> @@ -5,6 +5,7 @@ >>>>> >>>>> #include <dt-bindings/clock/qcom,rpmh.h> >>>>> #include <dt-bindings/clock/qcom,sm8450-videocc.h> >>>>> +#include <dt-bindings/clock/qcom,sm8550-camcc.h> >>>>> #include <dt-bindings/clock/qcom,sm8550-gcc.h> >>>>> #include <dt-bindings/clock/qcom,sm8550-gpucc.h> >>>>> #include <dt-bindings/clock/qcom,sm8550-tcsr.h> >>>>> @@ -2419,6 +2420,20 @@ videocc: clock-controller@aaf0000 { >>>>> #power-domain-cells = <1>; >>>>> }; >>>>> >>>>> + camcc: clock-controller@ade0000 { >>>>> + compatible = "qcom,sm8550-camcc"; >>>>> + reg = <0 0x0ade0000 0 0x20000>; >>>>> + clocks = <&gcc GCC_CAMERA_AHB_CLK>, >>>>> + <&bi_tcxo_div2>, >>>>> + <&bi_tcxo_ao_div2>, >>>>> + <&sleep_clk>; >>>>> + power-domains = <&rpmhpd SM8550_MMCX>; >>>> I see that both MMCX ("mmcx.lvl") and MXC ("mxc.lvl") (and MX, FWIW) >>>> are consumed on msm-5.15, with the latter one powering camcc PLLs.. >>>> >>>> How are they related? Is that resolved internally or does it need >>>> manual intervention? >>>> >>>> Konrad >>> >>> These are just different voltage rails, camcc clocks are powered by MMCX >>> rail and camcc pll's are powered by MXC rail. Consumer drivers need to >>> take care of voting on these rails properly based on the frequency of >>> clocks requested. >> >> Which rail powers registers of the camcc? Which rail is required to >> read PLL registers? >> > MMCX rail is required to access camcc registers, both MMCX and MXC are required to read PLL registers. MXC rail should be left ON from bootloaders during bootup and hence does not require explicit voting. That's a bad approach. We have a sync_state callback in rpmhpd that kills unused-from-linux-POV power rails, so Linux should be made aware of any and all requirements there. Konrad > > Thanks, > Jagadeesh > >>> >>> Thanks, >>> Jagadeesh >>> >>>>> + required-opps = <&rpmhpd_opp_low_svs>; >>>>> + #clock-cells = <1>; >>>>> + #reset-cells = <1>; >>>>> + #power-domain-cells = <1>; >>>>> + }; >>>>> + >>>>> mdss: display-subsystem@ae00000 { >>>>> compatible = "qcom,sm8550-mdss"; >>>>> reg = <0 0x0ae00000 0 0x1000>; >> >> >>
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 75cd374943eb..4d2d610fc66a 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -5,6 +5,7 @@ #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/clock/qcom,sm8450-videocc.h> +#include <dt-bindings/clock/qcom,sm8550-camcc.h> #include <dt-bindings/clock/qcom,sm8550-gcc.h> #include <dt-bindings/clock/qcom,sm8550-gpucc.h> #include <dt-bindings/clock/qcom,sm8550-tcsr.h> @@ -2419,6 +2420,20 @@ videocc: clock-controller@aaf0000 { #power-domain-cells = <1>; }; + camcc: clock-controller@ade0000 { + compatible = "qcom,sm8550-camcc"; + reg = <0 0x0ade0000 0 0x20000>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&sleep_clk>; + power-domains = <&rpmhpd SM8550_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + mdss: display-subsystem@ae00000 { compatible = "qcom,sm8550-mdss"; reg = <0 0x0ae00000 0 0x1000>;