From patchwork Fri Jun 9 11:50:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagadeesh Kona X-Patchwork-Id: 13273773 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6BC6BC7EE43 for ; Fri, 9 Jun 2023 11:52:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240252AbjFILwu (ORCPT ); Fri, 9 Jun 2023 07:52:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43506 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239688AbjFILwW (ORCPT ); Fri, 9 Jun 2023 07:52:22 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5BDA9358E; Fri, 9 Jun 2023 04:51:50 -0700 (PDT) Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 359BEdIo005928; Fri, 9 Jun 2023 11:51:46 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=IECLb9zryZkXqyOg1JHXaZ4TqcSXmpbvKhYFbmx8ikg=; b=XWiqJqGy5U5/wCj8PfLXKUJ+Rh/ct8zVw0xuNgNfeHFqyAe2l8JYhj+PupftLT5CYoRX Q4NlnNM9rglysEm6XM9KW9YsgNWEhDMYDPGycW57GUoaFpbxcewczihS4BwslQpce/Gx hAW+Vp1r7cnvUVOjczjG/SnJ9JI5EM9LGAQv/7graFs8YBV8bvb6SIwdYKVvSDDE5HrJ dJHxuS13QPorH9Kkn5Jm1ZeGVK63Ldr5+X9jOucc59W6zkSEecIi6iBG96f9CiIEDZlN RKOSYCcNWZptprlQqRqS6MmeCgRfSivYZZcR6JmnoPVMQIYdhM+18SnDPiPkyXrPcu/Q pw== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3r3nwesd3m-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 09 Jun 2023 11:51:45 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 359Bpi11000630 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 9 Jun 2023 11:51:44 GMT Received: from hu-jkona-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Fri, 9 Jun 2023 04:51:39 -0700 From: Jagadeesh Kona To: Andy Gross , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Bjorn Andersson , Vladimir Zapolskiy , , , , , Taniya Das , "Jagadeesh Kona" , Satya Priya Kakitapalli , Imran Shaik , "Ajit Pandey" Subject: [PATCH V4 4/4] arm64: dts: qcom: sm8550: Add camera clock controller Date: Fri, 9 Jun 2023 17:20:58 +0530 Message-ID: <20230609115058.9059-5-quic_jkona@quicinc.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230609115058.9059-1-quic_jkona@quicinc.com> References: <20230609115058.9059-1-quic_jkona@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: jsBby-q7fErqsDWRAXRFGgxa9QIO27ln X-Proofpoint-ORIG-GUID: jsBby-q7fErqsDWRAXRFGgxa9QIO27ln X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-09_08,2023-06-09_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 mlxlogscore=999 phishscore=0 priorityscore=1501 suspectscore=0 clxscore=1015 spamscore=0 adultscore=0 mlxscore=0 lowpriorityscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2306090100 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add device node for camera clock controller on Qualcomm SM8550 platform. Signed-off-by: Taniya Das Signed-off-by: Jagadeesh Kona --- Changes since V3: - No changes Changes since V2: - No changes Changes since V1: - Padded non-zero address part to 8 hex digits arch/arm64/boot/dts/qcom/sm8550.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 75cd374943eb..4d2d610fc66a 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -2419,6 +2420,20 @@ videocc: clock-controller@aaf0000 { #power-domain-cells = <1>; }; + camcc: clock-controller@ade0000 { + compatible = "qcom,sm8550-camcc"; + reg = <0 0x0ade0000 0 0x20000>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&sleep_clk>; + power-domains = <&rpmhpd SM8550_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + mdss: display-subsystem@ae00000 { compatible = "qcom,sm8550-mdss"; reg = <0 0x0ae00000 0 0x1000>;