| Message ID | 20230613125852.211636-4-xingyu.wu@starfivetech.com (mailing list archive) |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | Add PLL clocks driver and syscon for StarFive JH7110 SoC | expand |
On 13/06/2023 14:58, Xingyu Wu wrote: > Add optional PLL clock inputs from PLL clock generator. Are you sure that PLLs are optional? Usually they are not... > > Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> > --- > .../clock/starfive,jh7110-syscrg.yaml | 56 +++++++++++++++++++ > 1 file changed, 56 insertions(+) > > diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml > index 84373ae31644..5536e5f9e20b 100644 > --- a/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml > +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml > @@ -39,6 +39,33 @@ properties: > - description: External TDM clock > - description: External audio master clock > > + - items: > + - description: Main Oscillator (24 MHz) > + - description: GMAC1 RMII reference or GMAC1 RGMII RX > + - description: External I2S TX bit clock > + - description: External I2S TX left/right channel clock > + - description: External I2S RX bit clock > + - description: External I2S RX left/right channel clock > + - description: External TDM clock > + - description: External audio master clock > + - description: PLL0 > + - description: PLL1 > + - description: PLL2 Add these three to the existing entry with minItems. > + > + - items: > + - description: Main Oscillator (24 MHz) > + - description: GMAC1 RMII reference > + - description: GMAC1 RGMII RX > + - description: External I2S TX bit clock > + - description: External I2S TX left/right channel clock > + - description: External I2S RX bit clock > + - description: External I2S RX left/right channel clock > + - description: External TDM clock > + - description: External audio master clock > + - description: PLL0 > + - description: PLL1 > + - description: PLL2 Add these three to the existing entry with minItems. > + > clock-names: > oneOf: > - items: > @@ -64,6 +91,35 @@ properties: > - const: tdm_ext > - const: mclk_ext > > + - items: > + - const: osc > + - enum: > + - gmac1_rmii_refin > + - gmac1_rgmii_rxin > + - const: i2stx_bclk_ext > + - const: i2stx_lrck_ext > + - const: i2srx_bclk_ext > + - const: i2srx_lrck_ext > + - const: tdm_ext > + - const: mclk_ext > + - const: pll0_out > + - const: pll1_out > + - const: pll2_out Add these three to the existing entry with minItems. > + > + - items: > + - const: osc > + - const: gmac1_rmii_refin > + - const: gmac1_rgmii_rxin > + - const: i2stx_bclk_ext > + - const: i2stx_lrck_ext > + - const: i2srx_bclk_ext > + - const: i2srx_lrck_ext > + - const: tdm_ext > + - const: mclk_ext > + - const: pll0_out > + - const: pll1_out > + - const: pll2_out Add these three to the existing entry with minItems. Best regards, Krzysztof
On Tue, Jun 13, 2023 at 08:34:25PM +0200, Krzysztof Kozlowski wrote: > On 13/06/2023 14:58, Xingyu Wu wrote: > > Add optional PLL clock inputs from PLL clock generator. > > Are you sure that PLLs are optional? Usually they are not... They're not. What's happening here is the original binding was defined without these clocks (obviously, since they're only being added now) so for the driver they are still "optional" to keep compatibility. In mainline, the driver takes the "osc" input and registers some fixed-factor clocks to mimic these PLLs & after this patchset that is only done as a fallback if the clock inputs to the clock controller, from the PLLs, are missing. They should not be optional in the dt-binding because they're not optional in the hardware afaik! Cheers, Conor.
diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml index 84373ae31644..5536e5f9e20b 100644 --- a/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml @@ -39,6 +39,33 @@ properties: - description: External TDM clock - description: External audio master clock + - items: + - description: Main Oscillator (24 MHz) + - description: GMAC1 RMII reference or GMAC1 RGMII RX + - description: External I2S TX bit clock + - description: External I2S TX left/right channel clock + - description: External I2S RX bit clock + - description: External I2S RX left/right channel clock + - description: External TDM clock + - description: External audio master clock + - description: PLL0 + - description: PLL1 + - description: PLL2 + + - items: + - description: Main Oscillator (24 MHz) + - description: GMAC1 RMII reference + - description: GMAC1 RGMII RX + - description: External I2S TX bit clock + - description: External I2S TX left/right channel clock + - description: External I2S RX bit clock + - description: External I2S RX left/right channel clock + - description: External TDM clock + - description: External audio master clock + - description: PLL0 + - description: PLL1 + - description: PLL2 + clock-names: oneOf: - items: @@ -64,6 +91,35 @@ properties: - const: tdm_ext - const: mclk_ext + - items: + - const: osc + - enum: + - gmac1_rmii_refin + - gmac1_rgmii_rxin + - const: i2stx_bclk_ext + - const: i2stx_lrck_ext + - const: i2srx_bclk_ext + - const: i2srx_lrck_ext + - const: tdm_ext + - const: mclk_ext + - const: pll0_out + - const: pll1_out + - const: pll2_out + + - items: + - const: osc + - const: gmac1_rmii_refin + - const: gmac1_rgmii_rxin + - const: i2stx_bclk_ext + - const: i2stx_lrck_ext + - const: i2srx_bclk_ext + - const: i2srx_lrck_ext + - const: tdm_ext + - const: mclk_ext + - const: pll0_out + - const: pll1_out + - const: pll2_out + '#clock-cells': const: 1 description:
Add optional PLL clock inputs from PLL clock generator. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> --- .../clock/starfive,jh7110-syscrg.yaml | 56 +++++++++++++++++++ 1 file changed, 56 insertions(+)