| Message ID | 20230613125852.211636-8-xingyu.wu@starfivetech.com (mailing list archive) |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | Add PLL clocks driver and syscon for StarFive JH7110 SoC | expand |
On Tue, Jun 13, 2023 at 08:58:52PM +0800, Xingyu Wu wrote: > Modify the SYSCRG node to add PLL clocks input from > PLL clocks driver. > > Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Cheers, Conor.
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 11dd4c9d64b0..cdfd036a0e6c 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -452,12 +452,16 @@ syscrg: clock-controller@13020000 { <&gmac1_rgmii_rxin>, <&i2stx_bclk_ext>, <&i2stx_lrck_ext>, <&i2srx_bclk_ext>, <&i2srx_lrck_ext>, - <&tdm_ext>, <&mclk_ext>; + <&tdm_ext>, <&mclk_ext>, + <&pllclk JH7110_CLK_PLL0_OUT>, + <&pllclk JH7110_CLK_PLL1_OUT>, + <&pllclk JH7110_CLK_PLL2_OUT>; clock-names = "osc", "gmac1_rmii_refin", "gmac1_rgmii_rxin", "i2stx_bclk_ext", "i2stx_lrck_ext", "i2srx_bclk_ext", "i2srx_lrck_ext", - "tdm_ext", "mclk_ext"; + "tdm_ext", "mclk_ext", + "pll0_out", "pll1_out", "pll2_out"; #clock-cells = <1>; #reset-cells = <1>; };
Modify the SYSCRG node to add PLL clocks input from PLL clocks driver. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> --- arch/riscv/boot/dts/starfive/jh7110.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-)