diff --git a/drivers/clk/clk-fractional-divider_test.c b/drivers/clk/clk-fractional-divider_test.c
new file mode 100644
index 000000000000..0ea6b1ae85a8
--- /dev/null
+++ b/drivers/clk/clk-fractional-divider_test.c
@@ -0,0 +1,196 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Kunit test for clock fractional divider
+ */
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+
+/* Needed for clk_hw_get_clk() */
+#include "clk.h"
+
+/* Needed for clk_fractional_divider_ops */
+#include "clk-fractional-divider.h"
+
+#include <kunit/test.h>
+
+u32 fdregsim;
+
+static int clk_fd_test_init(struct kunit *test)
+{
+	struct clk_hw *hw;
+
+	hw = clk_hw_register_fractional_divider(NULL, "test_fd", NULL,
+						0,     /* flags */
+						&fdregsim,
+						0, 2,  /* mshift, mwidth */
+						8, 3,  /* nshift, nwidth */
+						0,     /* clk_divider_flags */
+						NULL); /* spinlock */
+	if (!hw)
+		return -ENOMEM;
+	else if (IS_ERR_VALUE(hw))
+		return PTR_ERR(hw);
+
+	test->priv = hw;
+	return 0;
+}
+
+static void clk_fd_test_exit(struct kunit *test)
+{
+	struct clk_hw *hw = test->priv;
+
+	clk_hw_unregister(hw);
+}
+
+/*
+ * Test the maximum divisor case for fd clock without flags.
+ *
+ * Prerequisites:
+ * - Requested rate is 240MHz.
+ * - Parent runs at 10 times the rate of the requested rate (2.4GHz).
+ * - m and n are 2 and 3 bits wide respectively.
+ * - The clock has no flags set, hence
+ *    - the maximum value for the numerator is 3
+ *    - the maximum value for the denominator is 7
+ *
+ * Expected result:
+ * Expect the highest possible divisor to be used in order to get as close as possible to the
+ * requested rate, resulting in the following rounded rate:
+ *         rounded_rate = parent_rate / 7.
+ */
+static void clk_fd_test_round_rate_max_div(struct kunit *test)
+{
+	struct clk_hw *hw = test->priv;
+	struct clk *clk = clk_hw_get_clk(hw, NULL);
+	unsigned long rate, parent_rate, rounded_rate;
+
+	rate = 240000000;
+	parent_rate = 10 * rate;
+
+	rounded_rate = clk_fractional_divider_ops.round_rate(hw, rate, &parent_rate);
+	/* This test case assumes that the round_rate operation does not change the parent */
+	KUNIT_ASSERT_EQ(test, parent_rate, 10 * rate);
+	/* Make sure the highest possible divisor was used */
+	KUNIT_EXPECT_EQ(test, rounded_rate, parent_rate / 7);
+
+	clk_put(clk);
+}
+
+/*
+ * Test the maximum multiplier case for fd clock without flags.
+ *
+ * Prerequisites:
+ * - Requested rate is 240MHz.
+ * - Parent runs at 7/4th the rate of the requested rate (420MHz).
+ * - m and n are 2 and 3 bits wide respectively.
+ * - The clock has no flags set, hence
+ *    - the maximum value for the numerator is 3
+ *    - the maximum value for the denominator is 7
+ *
+ * Expected result:
+ * Ideally the parent rate must be multiplied by 4 and divided by 7. But the highest possible
+ * multiplier is 3. So, the closest rate is not 4/7th of the parent rate, but 3/5th (252 MHz).
+ */
+static void clk_fd_test_round_rate_max_mul(struct kunit *test)
+{
+	struct clk_hw *hw = test->priv;
+	unsigned long rate, parent_rate, rounded_rate;
+
+	rate = 240000000;
+	parent_rate = 240000000 * 7 / 4;
+
+	rounded_rate = clk_fractional_divider_ops.round_rate(hw, rate, &parent_rate);
+	/* This test case assumes that the round_rate operation does not change the parent */
+	KUNIT_ASSERT_EQ(test, parent_rate, rate * 7 / 4);
+	/* Make sure the highest possible multiplier was used */
+	KUNIT_EXPECT_EQ(test, rounded_rate, parent_rate * 3 / 5);
+}
+
+/*
+ * Test the maximum divisor case for zero based fd clock.
+ *
+ * Prerequisites:
+ * - Requested rate is 240MHz.
+ * - Parent runs at 10 times the rate of the requested rate (2.4 GHz).
+ * - m and n are 2 and 3 bits wide respectively.
+ * - The clock is zero based, hence
+ *    - the maximum value for the numerator is 4
+ *    - the maximum value for the denominator is 8
+ *
+ * Expected result:
+ * Expect the highest possible divisor to be used resulting in the following rounded rate:
+ *         rounded_rate = parent_rate / 8.
+ */
+static void clk_fd_test_round_rate_max_div_zero_based(struct kunit *test)
+{
+	struct clk_hw *hw = test->priv;
+	unsigned long rate, parent_rate, rounded_rate;
+	struct clk_fractional_divider *fd = to_clk_fd(hw);
+
+	fd->flags = CLK_FRAC_DIVIDER_ZERO_BASED;
+
+	rate = 240000000;
+	parent_rate = 10 * rate;
+
+	rounded_rate = clk_fractional_divider_ops.round_rate(hw, rate, &parent_rate);
+	/* This test case assumes that the round_rate operation does not change the parent */
+	KUNIT_ASSERT_EQ(test, parent_rate, 10 * rate);
+	/* Make sure the highest possible divisor was used */
+	KUNIT_EXPECT_EQ(test, rounded_rate, parent_rate / 8);
+}
+
+/*
+ * Test the maximum multiplier case for fd clock without flags.
+ *
+ * Prerequisites:
+ * - Requested rate is 240MHz.
+ * - Parent runs at 7/4th the rate of the requested rate (420MHz).
+ * - m and n are 2 and 3 bits wide respectively.
+ * - The clock is zero based, hence
+ *    - the maximum value for the numerator is 4
+ *    - the maximum value for the denominator is 8
+ *
+ * Expected result:
+ * Ideally the parent rate must be multiplied by 4 and divided by seven. And since for a zero based
+ * clock 4 is actually the highest possible multiplier the exact rate can be reached.
+ */
+static void clk_fd_test_round_rate_max_mul_zero_based(struct kunit *test)
+{
+	struct clk_hw *hw = test->priv;
+	unsigned long rate, parent_rate, rounded_rate;
+	struct clk_fractional_divider *fd = to_clk_fd(hw);
+
+	fd->flags = CLK_FRAC_DIVIDER_ZERO_BASED;
+
+	rate = 240000000;
+	parent_rate = 240000000 * 7 / 4;
+
+	rounded_rate = clk_fractional_divider_ops.round_rate(hw, rate, &parent_rate);
+	/* This test case assumes that the round_rate operation does not change the parent */
+	KUNIT_ASSERT_EQ(test, parent_rate, rate * 7 / 4);
+	/* Make sure the highest possible multiplier was used */
+	KUNIT_EXPECT_EQ(test, rounded_rate, rate);
+}
+
+static struct kunit_case clk_fd_test_cases[] = {
+	KUNIT_CASE(clk_fd_test_round_rate_max_div),
+	KUNIT_CASE(clk_fd_test_round_rate_max_mul),
+	KUNIT_CASE(clk_fd_test_round_rate_max_div_zero_based),
+	KUNIT_CASE(clk_fd_test_round_rate_max_mul_zero_based),
+	{}
+};
+
+/*
+ * Test suite for a fractional divider clock.
+ */
+static struct kunit_suite clk_fd_test_suite = {
+	.name = "clk-fd-test",
+	.init = clk_fd_test_init,
+	.exit = clk_fd_test_exit,
+	.test_cases = clk_fd_test_cases,
+};
+
+kunit_test_suites(
+	&clk_fd_test_suite
+);
+MODULE_LICENSE("GPL");
