diff mbox series

[3/3] clk: imx: Add 519.75MHz frequency support for imx9 pll

Message ID 20230628061724.2056520-3-ping.bai@nxp.com (mailing list archive)
State Awaiting Upstream, archived
Headers show
Series [1/3] dt-bindings: clock: imx93: Add PDM IPG clk | expand

Commit Message

Jacky Bai June 28, 2023, 6:17 a.m. UTC 
For video pll, it may need 519.75MHz clock frequency for
the LVDS display usage. So add 519.75MHz frequency config
support for video pll.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
---
 drivers/clk/imx/clk-fracn-gppll.c | 1 +
 1 file changed, 1 insertion(+)

Comments

Peng Fan (OSS) June 30, 2023, 6:55 a.m. UTC | #1 
On 6/28/2023 2:17 PM, Jacky Bai wrote:
> For video pll, it may need 519.75MHz clock frequency for
> the LVDS display usage. So add 519.75MHz frequency config
> support for video pll.
> 
> Signed-off-by: Jacky Bai<ping.bai@nxp.com>

Reviewed-by: Peng Fan <peng.fan@nxp.com>
diff mbox series

Patch

diff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-gppll.c
index c54f9999da04..44462ab50e51 100644
--- a/drivers/clk/imx/clk-fracn-gppll.c
+++ b/drivers/clk/imx/clk-fracn-gppll.c
@@ -81,6 +81,7 @@  static const struct imx_fracn_gppll_rate_table fracn_tbl[] = {
 	PLL_FRACN_GP(650000000U, 162, 50, 100, 0, 6),
 	PLL_FRACN_GP(594000000U, 198, 0, 1, 0, 8),
 	PLL_FRACN_GP(560000000U, 140, 0, 1, 0, 6),
+	PLL_FRACN_GP(519750000U, 173, 25, 100, 1, 8),
 	PLL_FRACN_GP(498000000U, 166, 0, 1, 0, 8),
 	PLL_FRACN_GP(484000000U, 121, 0, 1, 0, 6),
 	PLL_FRACN_GP(445333333U, 167, 0, 1, 0, 9),