| Message ID | 20230704064610.292603-7-xingyu.wu@starfivetech.com (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Headers | show |
| Series | Add PLL clocks driver and syscon for StarFive JH7110 SoC | expand |
On Tue, 4 Jul 2023 at 08:49, Xingyu Wu <xingyu.wu@starfivetech.com> wrote: > > From: William Qiu <william.qiu@starfivetech.com> > > Add stg_syscon/sys_syscon/aon_syscon/PLL nodes for JH7110 SoC. > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > Co-developed-by: Xingyu Wu <xingyu.wu@starfivetech.com> > Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> > Signed-off-by: William Qiu <william.qiu@starfivetech.com> > --- > arch/riscv/boot/dts/starfive/jh7110.dtsi | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) > > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi > index 4c5fdb905da8..11dd4c9d64b0 100644 > --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi > @@ -353,6 +353,11 @@ i2c2: i2c@10050000 { > status = "disabled"; > }; > > + stg_syscon: syscon@10240000 { > + compatible = "starfive,jh7110-stg-syscon", "syscon"; > + reg = <0x0 0x10240000 0x0 0x1000>; > + }; > + > uart3: serial@12000000 { > compatible = "snps,dw-apb-uart"; > reg = <0x0 0x12000000 0x0 0x10000>; > @@ -457,6 +462,17 @@ syscrg: clock-controller@13020000 { > #reset-cells = <1>; > }; > > + sys_syscon: syscon@13030000 { > + compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd"; > + reg = <0x0 0x13030000 0x0 0x1000>; > + > + pllclk: clock-controller { Maybe call the handle "pll", so the references can be just <&pll 0>, <&pll 1> and <&pll 2> if you choose to drop the JH7110_PLLCLK_PLL?_OUT defines. In any case: Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> > + compatible = "starfive,jh7110-pll"; > + clocks = <&osc>; > + #clock-cells = <1>; > + }; > + }; > + > sysgpio: pinctrl@13040000 { > compatible = "starfive,jh7110-sys-pinctrl"; > reg = <0x0 0x13040000 0x0 0x10000>; > @@ -486,6 +502,12 @@ aoncrg: clock-controller@17000000 { > #reset-cells = <1>; > }; > > + aon_syscon: syscon@17010000 { > + compatible = "starfive,jh7110-aon-syscon", "syscon"; > + reg = <0x0 0x17010000 0x0 0x1000>; > + #power-domain-cells = <1>; > + }; > + > aongpio: pinctrl@17020000 { > compatible = "starfive,jh7110-aon-pinctrl"; > reg = <0x0 0x17020000 0x0 0x10000>; > -- > 2.25.1 >
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 4c5fdb905da8..11dd4c9d64b0 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -353,6 +353,11 @@ i2c2: i2c@10050000 { status = "disabled"; }; + stg_syscon: syscon@10240000 { + compatible = "starfive,jh7110-stg-syscon", "syscon"; + reg = <0x0 0x10240000 0x0 0x1000>; + }; + uart3: serial@12000000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x12000000 0x0 0x10000>; @@ -457,6 +462,17 @@ syscrg: clock-controller@13020000 { #reset-cells = <1>; }; + sys_syscon: syscon@13030000 { + compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd"; + reg = <0x0 0x13030000 0x0 0x1000>; + + pllclk: clock-controller { + compatible = "starfive,jh7110-pll"; + clocks = <&osc>; + #clock-cells = <1>; + }; + }; + sysgpio: pinctrl@13040000 { compatible = "starfive,jh7110-sys-pinctrl"; reg = <0x0 0x13040000 0x0 0x10000>; @@ -486,6 +502,12 @@ aoncrg: clock-controller@17000000 { #reset-cells = <1>; }; + aon_syscon: syscon@17010000 { + compatible = "starfive,jh7110-aon-syscon", "syscon"; + reg = <0x0 0x17010000 0x0 0x1000>; + #power-domain-cells = <1>; + }; + aongpio: pinctrl@17020000 { compatible = "starfive,jh7110-aon-pinctrl"; reg = <0x0 0x17020000 0x0 0x10000>;