| Message ID | 20230717023040.78860-6-xingyu.wu@starfivetech.com (mailing list archive) |
|---|---|
| State | Awaiting Upstream, archived |
| Headers | show |
| Series | Add PLL clocks driver and syscon for StarFive JH7110 SoC | expand |
On Mon, 17 Jul 2023 at 04:30, Xingyu Wu <xingyu.wu@starfivetech.com> wrote: > > Modify PLL clocks source to be got from DTS or > the fixed factor clocks. > > Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> > --- > drivers/clk/starfive/Kconfig | 1 + > .../clk/starfive/clk-starfive-jh7110-sys.c | 66 ++++++++++++------- > 2 files changed, 45 insertions(+), 22 deletions(-) > > diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig > index 5195f7be5213..978b78ec08b1 100644 > --- a/drivers/clk/starfive/Kconfig > +++ b/drivers/clk/starfive/Kconfig > @@ -35,6 +35,7 @@ config CLK_STARFIVE_JH7110_SYS > select AUXILIARY_BUS > select CLK_STARFIVE_JH71X0 > select RESET_STARFIVE_JH7110 if RESET_CONTROLLER > + select CLK_STARFIVE_JH7110_PLL > default ARCH_STARFIVE > help > Say yes here to support the system clock controller on the > diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c > index e6031345ef05..3884eff9fe93 100644 > --- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c > +++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c > @@ -7,6 +7,7 @@ > */ > > #include <linux/auxiliary_bus.h> > +#include <linux/clk.h> > #include <linux/clk-provider.h> > #include <linux/init.h> > #include <linux/io.h> > @@ -389,6 +390,7 @@ static int __init jh7110_syscrg_probe(struct platform_device *pdev) > struct jh71x0_clk_priv *priv; > unsigned int idx; > int ret; > + struct clk *pllclk; > > priv = devm_kzalloc(&pdev->dev, > struct_size(priv, reg, JH7110_SYSCLK_END), > @@ -402,28 +404,42 @@ static int __init jh7110_syscrg_probe(struct platform_device *pdev) > if (IS_ERR(priv->base)) > return PTR_ERR(priv->base); > > - /* > - * These PLL clocks are not actually fixed factor clocks and can be > - * controlled by the syscon registers of JH7110. They will be dropped > - * and registered in the PLL clock driver instead. > - */ > - /* 24MHz -> 1000.0MHz */ > - priv->pll[0] = devm_clk_hw_register_fixed_factor(priv->dev, "pll0_out", > - "osc", 0, 125, 3); > - if (IS_ERR(priv->pll[0])) > - return PTR_ERR(priv->pll[0]); > - > - /* 24MHz -> 1066.0MHz */ > - priv->pll[1] = devm_clk_hw_register_fixed_factor(priv->dev, "pll1_out", > - "osc", 0, 533, 12); > - if (IS_ERR(priv->pll[1])) > - return PTR_ERR(priv->pll[1]); > - > - /* 24MHz -> 1188.0MHz */ > - priv->pll[2] = devm_clk_hw_register_fixed_factor(priv->dev, "pll2_out", > - "osc", 0, 99, 2); > - if (IS_ERR(priv->pll[2])) > - return PTR_ERR(priv->pll[2]); > + /* Use fixed factor clocks if can not get the PLL clocks from DTS */ > + pllclk = clk_get(priv->dev, "pll0_out"); > + if (IS_ERR(pllclk)) { > + /* 24MHz -> 1000.0MHz */ > + priv->pll[0] = devm_clk_hw_register_fixed_factor(priv->dev, "pll0_out", > + "osc", 0, 125, 3); > + if (IS_ERR(priv->pll[0])) > + return PTR_ERR(priv->pll[0]); > + } else { > + clk_put(pllclk); > + priv->pll[0] = NULL; Not really important enough for a respin, but setting these to NULL is not needed as devm_kzalloc() already zeroes the memory allocated. In any case: Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> > + } > + > + pllclk = clk_get(priv->dev, "pll1_out"); > + if (IS_ERR(pllclk)) { > + /* 24MHz -> 1066.0MHz */ > + priv->pll[1] = devm_clk_hw_register_fixed_factor(priv->dev, "pll1_out", > + "osc", 0, 533, 12); > + if (IS_ERR(priv->pll[1])) > + return PTR_ERR(priv->pll[1]); > + } else { > + clk_put(pllclk); > + priv->pll[1] = NULL; > + } > + > + pllclk = clk_get(priv->dev, "pll2_out"); > + if (IS_ERR(pllclk)) { > + /* 24MHz -> 1188.0MHz */ > + priv->pll[2] = devm_clk_hw_register_fixed_factor(priv->dev, "pll2_out", > + "osc", 0, 99, 2); > + if (IS_ERR(priv->pll[2])) > + return PTR_ERR(priv->pll[2]); > + } else { > + clk_put(pllclk); > + priv->pll[2] = NULL; > + } > > for (idx = 0; idx < JH7110_SYSCLK_END; idx++) { > u32 max = jh7110_sysclk_data[idx].max; > @@ -462,6 +478,12 @@ static int __init jh7110_syscrg_probe(struct platform_device *pdev) > parents[i].fw_name = "tdm_ext"; > else if (pidx == JH7110_SYSCLK_MCLK_EXT) > parents[i].fw_name = "mclk_ext"; > + else if (pidx == JH7110_SYSCLK_PLL0_OUT && !priv->pll[0]) > + parents[i].fw_name = "pll0_out"; > + else if (pidx == JH7110_SYSCLK_PLL1_OUT && !priv->pll[1]) > + parents[i].fw_name = "pll1_out"; > + else if (pidx == JH7110_SYSCLK_PLL2_OUT && !priv->pll[2]) > + parents[i].fw_name = "pll2_out"; > else > parents[i].hw = priv->pll[pidx - JH7110_SYSCLK_PLL0_OUT]; > } > -- > 2.25.1 >
diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig index 5195f7be5213..978b78ec08b1 100644 --- a/drivers/clk/starfive/Kconfig +++ b/drivers/clk/starfive/Kconfig @@ -35,6 +35,7 @@ config CLK_STARFIVE_JH7110_SYS select AUXILIARY_BUS select CLK_STARFIVE_JH71X0 select RESET_STARFIVE_JH7110 if RESET_CONTROLLER + select CLK_STARFIVE_JH7110_PLL default ARCH_STARFIVE help Say yes here to support the system clock controller on the diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c index e6031345ef05..3884eff9fe93 100644 --- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c +++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c @@ -7,6 +7,7 @@ */ #include <linux/auxiliary_bus.h> +#include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/init.h> #include <linux/io.h> @@ -389,6 +390,7 @@ static int __init jh7110_syscrg_probe(struct platform_device *pdev) struct jh71x0_clk_priv *priv; unsigned int idx; int ret; + struct clk *pllclk; priv = devm_kzalloc(&pdev->dev, struct_size(priv, reg, JH7110_SYSCLK_END), @@ -402,28 +404,42 @@ static int __init jh7110_syscrg_probe(struct platform_device *pdev) if (IS_ERR(priv->base)) return PTR_ERR(priv->base); - /* - * These PLL clocks are not actually fixed factor clocks and can be - * controlled by the syscon registers of JH7110. They will be dropped - * and registered in the PLL clock driver instead. - */ - /* 24MHz -> 1000.0MHz */ - priv->pll[0] = devm_clk_hw_register_fixed_factor(priv->dev, "pll0_out", - "osc", 0, 125, 3); - if (IS_ERR(priv->pll[0])) - return PTR_ERR(priv->pll[0]); - - /* 24MHz -> 1066.0MHz */ - priv->pll[1] = devm_clk_hw_register_fixed_factor(priv->dev, "pll1_out", - "osc", 0, 533, 12); - if (IS_ERR(priv->pll[1])) - return PTR_ERR(priv->pll[1]); - - /* 24MHz -> 1188.0MHz */ - priv->pll[2] = devm_clk_hw_register_fixed_factor(priv->dev, "pll2_out", - "osc", 0, 99, 2); - if (IS_ERR(priv->pll[2])) - return PTR_ERR(priv->pll[2]); + /* Use fixed factor clocks if can not get the PLL clocks from DTS */ + pllclk = clk_get(priv->dev, "pll0_out"); + if (IS_ERR(pllclk)) { + /* 24MHz -> 1000.0MHz */ + priv->pll[0] = devm_clk_hw_register_fixed_factor(priv->dev, "pll0_out", + "osc", 0, 125, 3); + if (IS_ERR(priv->pll[0])) + return PTR_ERR(priv->pll[0]); + } else { + clk_put(pllclk); + priv->pll[0] = NULL; + } + + pllclk = clk_get(priv->dev, "pll1_out"); + if (IS_ERR(pllclk)) { + /* 24MHz -> 1066.0MHz */ + priv->pll[1] = devm_clk_hw_register_fixed_factor(priv->dev, "pll1_out", + "osc", 0, 533, 12); + if (IS_ERR(priv->pll[1])) + return PTR_ERR(priv->pll[1]); + } else { + clk_put(pllclk); + priv->pll[1] = NULL; + } + + pllclk = clk_get(priv->dev, "pll2_out"); + if (IS_ERR(pllclk)) { + /* 24MHz -> 1188.0MHz */ + priv->pll[2] = devm_clk_hw_register_fixed_factor(priv->dev, "pll2_out", + "osc", 0, 99, 2); + if (IS_ERR(priv->pll[2])) + return PTR_ERR(priv->pll[2]); + } else { + clk_put(pllclk); + priv->pll[2] = NULL; + } for (idx = 0; idx < JH7110_SYSCLK_END; idx++) { u32 max = jh7110_sysclk_data[idx].max; @@ -462,6 +478,12 @@ static int __init jh7110_syscrg_probe(struct platform_device *pdev) parents[i].fw_name = "tdm_ext"; else if (pidx == JH7110_SYSCLK_MCLK_EXT) parents[i].fw_name = "mclk_ext"; + else if (pidx == JH7110_SYSCLK_PLL0_OUT && !priv->pll[0]) + parents[i].fw_name = "pll0_out"; + else if (pidx == JH7110_SYSCLK_PLL1_OUT && !priv->pll[1]) + parents[i].fw_name = "pll1_out"; + else if (pidx == JH7110_SYSCLK_PLL2_OUT && !priv->pll[2]) + parents[i].fw_name = "pll2_out"; else parents[i].hw = priv->pll[pidx - JH7110_SYSCLK_PLL0_OUT]; }
Modify PLL clocks source to be got from DTS or the fixed factor clocks. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> --- drivers/clk/starfive/Kconfig | 1 + .../clk/starfive/clk-starfive-jh7110-sys.c | 66 ++++++++++++------- 2 files changed, 45 insertions(+), 22 deletions(-)