| Message ID | 20230728020810.29732-3-zhangqing@rock-chips.com (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Headers | show |
| Series | clk: rockchip: add GATE_LINK | expand |
diff --git a/include/dt-bindings/clock/rockchip,rk3588-cru.h b/include/dt-bindings/clock/rockchip,rk3588-cru.h index b5616bca7b44..864a321ab362 100644 --- a/include/dt-bindings/clock/rockchip,rk3588-cru.h +++ b/include/dt-bindings/clock/rockchip,rk3588-cru.h @@ -733,8 +733,9 @@ #define ACLK_AV1_PRE 718 #define PCLK_AV1_PRE 719 #define HCLK_SDIO_PRE 720 +#define PCLK_VO1GRF 721 -#define CLK_NR_CLKS (HCLK_SDIO_PRE + 1) +#define CLK_NR_CLKS (PCLK_VO1GRF + 1) /* scmi-clocks indices */
add PCLK_VO1GRF clk id. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> --- include/dt-bindings/clock/rockchip,rk3588-cru.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)