| Message ID | 20230807084744.1184791-1-m.felsch@pengutronix.de (mailing list archive) |
|---|---|
| State | Awaiting Upstream, archived |
| Headers | show |
| Series | [v2,1/2] clk: imx: pll14xx: align pdiv with reference manual | expand |
On 07.08.23 10:47, Marco Felsch wrote: > The PLL14xx hardware can be found on i.MX8M{M,N,P} SoCs and always come > with a 6-bit pre-divider. Neither the reference manuals nor the > datasheets of these SoCs do mention any restrictions. Furthermore the > current code doesn't respect the restrictions from the comment too. > > Therefore drop the restriction and align the max pre-divider (pdiv) > value to 63 to get more accurate frequencies. > > Fixes: b09c68dc57c9 ("clk: imx: pll14xx: Support dynamic rates") > Cc: stable@vger.kernel.org > Signed-off-by: Marco Felsch <m.felsch@pengutronix.de> > Reviewed-by: Abel Vesa <abel.vesa@linaro.org> > Reviewed-by: Adam Ford <aford173@gmail.com> > Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Tested-by: Ahmad Fatoum <a.fatoum@pengutronix.de> > --- > v2: > - Link: https://lore.kernel.org/all/20230714134938.2124861-1-m.felsch@pengutronix.de/ > - add fixes tag > > drivers/clk/imx/clk-pll14xx.c | 11 +++++------ > 1 file changed, 5 insertions(+), 6 deletions(-) > > diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c > index 7150c59bbfc9..dc6bc21dff41 100644 > --- a/drivers/clk/imx/clk-pll14xx.c > +++ b/drivers/clk/imx/clk-pll14xx.c > @@ -139,11 +139,10 @@ static void imx_pll14xx_calc_settings(struct clk_pll14xx *pll, unsigned long rat > /* > * Fractional PLL constrains: > * > - * a) 6MHz <= prate <= 25MHz > - * b) 1 <= p <= 63 (1 <= p <= 4 prate = 24MHz) > - * c) 64 <= m <= 1023 > - * d) 0 <= s <= 6 > - * e) -32768 <= k <= 32767 > + * a) 1 <= p <= 63 > + * b) 64 <= m <= 1023 > + * c) 0 <= s <= 6 > + * d) -32768 <= k <= 32767 > * > * fvco = (m * 65536 + k) * prate / (p * 65536) > */ > @@ -186,7 +185,7 @@ static void imx_pll14xx_calc_settings(struct clk_pll14xx *pll, unsigned long rat > } > > /* Finally calculate best values */ > - for (pdiv = 1; pdiv <= 7; pdiv++) { > + for (pdiv = 1; pdiv <= 63; pdiv++) { > for (sdiv = 0; sdiv <= 6; sdiv++) { > /* calc mdiv = round(rate * pdiv * 2^sdiv) / prate) */ > mdiv = DIV_ROUND_CLOSEST(rate * (pdiv << sdiv), prate);
On Mon, Aug 07, 2023 at 10:47:43AM +0200, Marco Felsch wrote: > The PLL14xx hardware can be found on i.MX8M{M,N,P} SoCs and always come > with a 6-bit pre-divider. Neither the reference manuals nor the > datasheets of these SoCs do mention any restrictions. Furthermore the > current code doesn't respect the restrictions from the comment too. > > Therefore drop the restriction and align the max pre-divider (pdiv) > value to 63 to get more accurate frequencies. > > Fixes: b09c68dc57c9 ("clk: imx: pll14xx: Support dynamic rates") > Cc: stable@vger.kernel.org > Signed-off-by: Marco Felsch <m.felsch@pengutronix.de> > Reviewed-by: Abel Vesa <abel.vesa@linaro.org> > Reviewed-by: Adam Ford <aford173@gmail.com> > Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Sascha > --- > v2: > - Link: https://lore.kernel.org/all/20230714134938.2124861-1-m.felsch@pengutronix.de/ > - add fixes tag > > drivers/clk/imx/clk-pll14xx.c | 11 +++++------ > 1 file changed, 5 insertions(+), 6 deletions(-) > > diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c > index 7150c59bbfc9..dc6bc21dff41 100644 > --- a/drivers/clk/imx/clk-pll14xx.c > +++ b/drivers/clk/imx/clk-pll14xx.c > @@ -139,11 +139,10 @@ static void imx_pll14xx_calc_settings(struct clk_pll14xx *pll, unsigned long rat > /* > * Fractional PLL constrains: > * > - * a) 6MHz <= prate <= 25MHz > - * b) 1 <= p <= 63 (1 <= p <= 4 prate = 24MHz) > - * c) 64 <= m <= 1023 > - * d) 0 <= s <= 6 > - * e) -32768 <= k <= 32767 > + * a) 1 <= p <= 63 > + * b) 64 <= m <= 1023 > + * c) 0 <= s <= 6 > + * d) -32768 <= k <= 32767 > * > * fvco = (m * 65536 + k) * prate / (p * 65536) > */ > @@ -186,7 +185,7 @@ static void imx_pll14xx_calc_settings(struct clk_pll14xx *pll, unsigned long rat > } > > /* Finally calculate best values */ > - for (pdiv = 1; pdiv <= 7; pdiv++) { > + for (pdiv = 1; pdiv <= 63; pdiv++) { > for (sdiv = 0; sdiv <= 6; sdiv++) { > /* calc mdiv = round(rate * pdiv * 2^sdiv) / prate) */ > mdiv = DIV_ROUND_CLOSEST(rate * (pdiv << sdiv), prate); > -- > 2.39.2 > >
On Mon, 07 Aug 2023 10:47:43 +0200, Marco Felsch wrote: > The PLL14xx hardware can be found on i.MX8M{M,N,P} SoCs and always come > with a 6-bit pre-divider. Neither the reference manuals nor the > datasheets of these SoCs do mention any restrictions. Furthermore the > current code doesn't respect the restrictions from the comment too. > > Therefore drop the restriction and align the max pre-divider (pdiv) > value to 63 to get more accurate frequencies. > > [...] Applied, thanks! [1/2] clk: imx: pll14xx: align pdiv with reference manual commit: 37cfd5e457cbdcd030f378127ff2d62776f641e7 [2/2] clk: imx: pll14xx: dynamically configure PLL for 393216000/361267200Hz commit: 72d00e560d10665e6139c9431956a87ded6e9880 Best regards,
diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index 7150c59bbfc9..dc6bc21dff41 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -139,11 +139,10 @@ static void imx_pll14xx_calc_settings(struct clk_pll14xx *pll, unsigned long rat /* * Fractional PLL constrains: * - * a) 6MHz <= prate <= 25MHz - * b) 1 <= p <= 63 (1 <= p <= 4 prate = 24MHz) - * c) 64 <= m <= 1023 - * d) 0 <= s <= 6 - * e) -32768 <= k <= 32767 + * a) 1 <= p <= 63 + * b) 64 <= m <= 1023 + * c) 0 <= s <= 6 + * d) -32768 <= k <= 32767 * * fvco = (m * 65536 + k) * prate / (p * 65536) */ @@ -186,7 +185,7 @@ static void imx_pll14xx_calc_settings(struct clk_pll14xx *pll, unsigned long rat } /* Finally calculate best values */ - for (pdiv = 1; pdiv <= 7; pdiv++) { + for (pdiv = 1; pdiv <= 63; pdiv++) { for (sdiv = 0; sdiv <= 6; sdiv++) { /* calc mdiv = round(rate * pdiv * 2^sdiv) / prate) */ mdiv = DIV_ROUND_CLOSEST(rate * (pdiv << sdiv), prate);
The PLL14xx hardware can be found on i.MX8M{M,N,P} SoCs and always come with a 6-bit pre-divider. Neither the reference manuals nor the datasheets of these SoCs do mention any restrictions. Furthermore the current code doesn't respect the restrictions from the comment too. Therefore drop the restriction and align the max pre-divider (pdiv) value to 63 to get more accurate frequencies. Fixes: b09c68dc57c9 ("clk: imx: pll14xx: Support dynamic rates") Cc: stable@vger.kernel.org Signed-off-by: Marco Felsch <m.felsch@pengutronix.de> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Adam Ford <aford173@gmail.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> --- v2: - Link: https://lore.kernel.org/all/20230714134938.2124861-1-m.felsch@pengutronix.de/ - add fixes tag drivers/clk/imx/clk-pll14xx.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-)