| Message ID | 20230809080047.19877-2-quic_luoj@quicinc.com (mailing list archive) |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | add clock controller of qca8386/qca8084 | expand |
On 9.08.2023 10:00, Luo Jie wrote: > Add the clk_branch2_qca8k_ops for supporting clock controller > where the hardware register is accessed by MDIO bus, and the > spin clock can't be used because of sleep during the MDIO > operation. > > The clock is enabled by the .prepare instead of .enable when > the clk_branch2_qca8k_ops is used. > > Signed-off-by: Luo Jie <quic_luoj@quicinc.com> > --- clk_branch2_mdio_ops? Konrad
On 8/10/2023 12:56 AM, Konrad Dybcio wrote: > On 9.08.2023 10:00, Luo Jie wrote: >> Add the clk_branch2_qca8k_ops for supporting clock controller >> where the hardware register is accessed by MDIO bus, and the >> spin clock can't be used because of sleep during the MDIO >> operation. >> >> The clock is enabled by the .prepare instead of .enable when >> the clk_branch2_qca8k_ops is used. >> >> Signed-off-by: Luo Jie <quic_luoj@quicinc.com> >> --- > clk_branch2_mdio_ops? > > Konrad okay, will update it to clk_branch2_mdio_ops, thanks Konrad.
diff --git a/drivers/clk/qcom/clk-branch.c b/drivers/clk/qcom/clk-branch.c index fc4735f74f0f..d07f2677c877 100644 --- a/drivers/clk/qcom/clk-branch.c +++ b/drivers/clk/qcom/clk-branch.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2013, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #include <linux/kernel.h> @@ -153,3 +154,10 @@ const struct clk_ops clk_branch_simple_ops = { .is_enabled = clk_is_enabled_regmap, }; EXPORT_SYMBOL_GPL(clk_branch_simple_ops); + +const struct clk_ops clk_branch2_qca8k_ops = { + .prepare = clk_branch2_enable, + .unprepare = clk_branch2_disable, + .is_prepared = clk_is_enabled_regmap, +}; +EXPORT_SYMBOL_GPL(clk_branch2_qca8k_ops); diff --git a/drivers/clk/qcom/clk-branch.h b/drivers/clk/qcom/clk-branch.h index 0cf800b9d08d..37b092bf4d79 100644 --- a/drivers/clk/qcom/clk-branch.h +++ b/drivers/clk/qcom/clk-branch.h @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* Copyright (c) 2013, The Linux Foundation. All rights reserved. */ +/* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef __QCOM_CLK_BRANCH_H__ #define __QCOM_CLK_BRANCH_H__ @@ -85,6 +86,7 @@ extern const struct clk_ops clk_branch_ops; extern const struct clk_ops clk_branch2_ops; extern const struct clk_ops clk_branch_simple_ops; extern const struct clk_ops clk_branch2_aon_ops; +extern const struct clk_ops clk_branch2_qca8k_ops; #define to_clk_branch(_hw) \ container_of(to_clk_regmap(_hw), struct clk_branch, clkr)
Add the clk_branch2_qca8k_ops for supporting clock controller where the hardware register is accessed by MDIO bus, and the spin clock can't be used because of sleep during the MDIO operation. The clock is enabled by the .prepare instead of .enable when the clk_branch2_qca8k_ops is used. Signed-off-by: Luo Jie <quic_luoj@quicinc.com> --- drivers/clk/qcom/clk-branch.c | 8 ++++++++ drivers/clk/qcom/clk-branch.h | 2 ++ 2 files changed, 10 insertions(+)