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Tue, 12 Sep 2023 09:14:48 +0000 From: "Peng Fan (OSS)" Date: Tue, 12 Sep 2023 17:19:01 +0800 Subject: [PATCH 3/7] clk: imx: imx8qxp: correct the enet clocks for i.MX8DXL Message-Id: <20230912-imx8-clk-v1-v1-3-69a34bcfcae1@nxp.com> References: <20230912-imx8-clk-v1-v1-0-69a34bcfcae1@nxp.com> In-Reply-To: <20230912-imx8-clk-v1-v1-0-69a34bcfcae1@nxp.com> To: Abel Vesa , Peng Fan , Michael Turquette , Stephen Boyd , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Jacky Bai , Dong Aisheng Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Shenwei Wang , Ranjani Vaidyanathan , Jason Liu X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1694510362; l=2559; i=peng.fan@nxp.com; s=20230812; h=from:subject:message-id; bh=J9ZzBj6jt1w7y8HEhTZBc14V86K3cqrQupVPS8cfPAI=; b=4BMk91mGwweVGwKpDpoVXKUPn3qe19ag0rLU32BZ94Ox+sA0vXiMj6qPTTsQlGbHoHzrUpS2k dVbcQ511CaGDpUJmFlQml+X9+W0dWrAviifB/WMP8SnuvujV8AGrf+e X-Developer-Key: i=peng.fan@nxp.com; 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Using the clock device compatible string to identify the platform and only initialize the enetX_rgmii_rx_clk clock for non i.MX8DXL platform. Signed-off-by: Shenwei Wang Reviewed-by: Ranjani Vaidyanathan Reviewed-by: Jacky Bai Acked-by: Jason Liu Signed-off-by: Peng Fan --- drivers/clk/imx/clk-imx8qxp.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c index 4020aa4b79bf..41f0a45aa162 100644 --- a/drivers/clk/imx/clk-imx8qxp.c +++ b/drivers/clk/imx/clk-imx8qxp.c @@ -90,6 +90,11 @@ static const char * const pi_pll0_sels[] = { "clk_dummy", }; +static inline bool clk_on_imx8dxl(struct device_node *node) +{ + return of_device_is_compatible(node, "fsl,imx8dxl-clk"); +} + static int imx8qxp_clk_probe(struct platform_device *pdev) { struct device_node *ccm_node = pdev->dev.of_node; @@ -169,13 +174,15 @@ static int imx8qxp_clk_probe(struct platform_device *pdev) imx_clk_mux_gpr_scu("enet0_rgmii_txc_sel", enet0_rgmii_txc_sels, ARRAY_SIZE(enet0_rgmii_txc_sels), IMX_SC_R_ENET_0, IMX_SC_C_TXCLK); imx_clk_scu("enet0_bypass_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_BYPASS); imx_clk_gate_gpr_scu("enet0_ref_50_clk", "clk_dummy", IMX_SC_R_ENET_0, IMX_SC_C_DISABLE_50, true); - imx_clk_scu("enet0_rgmii_rx_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_MISC0); + if (!clk_on_imx8dxl(ccm_node)) { + imx_clk_scu("enet0_rgmii_rx_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_MISC0); + imx_clk_scu("enet1_rgmii_rx_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_MISC0); + } imx_clk_scu("enet1_root_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_PER); imx_clk_divider_gpr_scu("enet1_ref_div", "enet1_root_clk", IMX_SC_R_ENET_1, IMX_SC_C_CLKDIV); imx_clk_mux_gpr_scu("enet1_rgmii_txc_sel", enet1_rgmii_txc_sels, ARRAY_SIZE(enet1_rgmii_txc_sels), IMX_SC_R_ENET_1, IMX_SC_C_TXCLK); imx_clk_scu("enet1_bypass_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_BYPASS); imx_clk_gate_gpr_scu("enet1_ref_50_clk", "clk_dummy", IMX_SC_R_ENET_1, IMX_SC_C_DISABLE_50, true); - imx_clk_scu("enet1_rgmii_rx_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_MISC0); imx_clk_scu("gpmi_io_clk", IMX_SC_R_NAND, IMX_SC_PM_CLK_MST_BUS); imx_clk_scu("gpmi_bch_clk", IMX_SC_R_NAND, IMX_SC_PM_CLK_PER); imx_clk_scu("usb3_aclk_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_PER);