@@ -77,7 +77,7 @@ struct imx8_acm_priv {
static const struct clk_parent_data imx8qm_aud_clk_sels[] = {
{ .fw_name = "aud_rec_clk0_lpcg_clk" },
{ .fw_name = "aud_rec_clk1_lpcg_clk" },
- { .fw_name = "mlb_clk" },
+ { .fw_name = "dummy" },
{ .fw_name = "hdmi_rx_mclk" },
{ .fw_name = "ext_aud_mclk0" },
{ .fw_name = "ext_aud_mclk1" },
@@ -103,7 +103,7 @@ static const struct clk_parent_data imx8qm_aud_clk_sels[] = {
static const struct clk_parent_data imx8qm_mclk_out_sels[] = {
{ .fw_name = "aud_rec_clk0_lpcg_clk" },
{ .fw_name = "aud_rec_clk1_lpcg_clk" },
- { .fw_name = "mlb_clk" },
+ { .fw_name = "dummy" },
{ .fw_name = "hdmi_rx_mclk" },
{ .fw_name = "spdif0_rx" },
{ .fw_name = "spdif1_rx" },
@@ -122,7 +122,7 @@ static const struct clk_parent_data imx8qm_asrc_mux_clk_sels[] = {
{ .fw_name = "sai4_rx_bclk" },
{ .fw_name = "sai5_tx_bclk" },
{ .index = -1 },
- { .fw_name = "mlb_clk" },
+ { .fw_name = "dummy" },
};
@@ -47,7 +47,6 @@ static u32 imx8dxl_clk_scu_rsrc_table[] = {
IMX_SC_R_SDHC_2,
IMX_SC_R_ENET_0,
IMX_SC_R_ENET_1,
- IMX_SC_R_MLB_0,
IMX_SC_R_USB_1,
IMX_SC_R_NAND,
IMX_SC_R_M4_0_UART,
@@ -65,7 +65,6 @@ static const u32 imx8qm_clk_scu_rsrc_table[] = {
IMX_SC_R_SDHC_2,
IMX_SC_R_ENET_0,
IMX_SC_R_ENET_1,
- IMX_SC_R_MLB_0,
IMX_SC_R_USB_2,
IMX_SC_R_NAND,
IMX_SC_R_LVDS_0,
@@ -42,7 +42,6 @@
#define CONN_ENET_0_LPCG 0x30000
#define CONN_ENET_1_LPCG 0x40000
#define CONN_DTCP_LPCG 0x50000
-#define CONN_MLB_LPCG 0x60000
#define CONN_USB_2_LPCG 0x70000
#define CONN_USB_3_LPCG 0x80000
#define CONN_NAND_LPCG 0x90000
@@ -54,7 +54,6 @@ static const u32 imx8qxp_clk_scu_rsrc_table[] = {
IMX_SC_R_SDHC_2,
IMX_SC_R_ENET_0,
IMX_SC_R_ENET_1,
- IMX_SC_R_MLB_0,
IMX_SC_R_USB_2,
IMX_SC_R_NAND,
IMX_SC_R_LVDS_0,