[3/4] clk: imx: composite-7ulp: Add some delay before deassert the reset

Commit Message

Peng Fan (OSS) Sept. 12, 2023, 1:16 p.m. UTC

From: Jacky Bai <[e-mail]>

Some of the PCCs on i.MX8ULP have a sw_rst bit to control
the peripheral reset through SW method. For peripherals like GPU
that need sync reset, some delay is necessary befere & after release
the reset to make sure the HW is reset into known status. So add
some delay before & after release reset.

Reviewed-by: Peng Fan <[e-mail]>
Signed-off-by: Jacky Bai <[e-mail]>
Signed-off-by: Peng Fan <[e-mail]>
---
 drivers/clk/imx/clk-composite-7ulp.c | 7 +++++++
 1 file changed, 7 insertions(+)

Patch

diff --git a/drivers/clk/imx/clk-composite-7ulp.c b/drivers/clk/imx/clk-composite-7ulp.c
index e208ddc51133..715a60f81bce 100644
--- a/drivers/clk/imx/clk-composite-7ulp.c
+++ b/drivers/clk/imx/clk-composite-7ulp.c
@@ -7,6 +7,7 @@ 
 
 #include <linux/bits.h>
 #include <linux/clk-provider.h>
+#include <linux/delay.h>
 #include <linux/err.h>
 #include <linux/io.h>
 #include <linux/slab.h>
@@ -35,6 +36,9 @@  static int pcc_gate_enable(struct clk_hw *hw)
 	if (ret)
 		return ret;
 
+	/* wait before release reset */
+	udelay(1);
+
 	spin_lock_irqsave(gate->lock, flags);
 	/*
 	 * release the sw reset for peripherals associated with
@@ -46,6 +50,9 @@  static int pcc_gate_enable(struct clk_hw *hw)
 
 	spin_unlock_irqrestore(gate->lock, flags);
 
+	/* wait sync reset done */
+	udelay(1);
+
 	return 0;
 }